Patents by Inventor Takashi Hirao

Takashi Hirao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9304906
    Abstract: According to one embodiment, a memory system includes non-volatile memory, a block management table that stores whether data in the non-volatile memory is valid or invalid in a unit of cluster, and a controller configured to execute compaction. In the block management table, first information related to likelihood that valid data within the block is invalidated is registered for each of the blocks. The controller is configured to select a block to be a target of the compaction based on the first information and use the selected block to execute the compaction.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: April 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroki Matsudaira, Takashi Hirao, Aurelien Nam Phong Tran
  • Patent number: 9251055
    Abstract: A memory system in embodiments includes a nonvolatile semiconductor memory that stores user data, a forward lookup address translation table and a reverse lookup address translation table, and a controller. The controller is configured to determine that the user data stored in the nonvolatile semiconductor memory is valid or invalid based on these two tables. The controller may perform data organizing of selecting data determined valid and rewriting the data in a new block. The controller may perform write processing and rewriting processing to the new block alternately at a predetermined ratio. The controller may determine whether a predetermined condition is satisfied on a basis of addresses included in write requests and write data in the MLC mode when the condition is satisfied and write data in the SLC mode when the condition is not satisfied.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 2, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Yonezawa, Takashi Hirao, Hirokuni Yano, Mitsunori Tadokoro, Hiroki Matsudaira, Akira Sawaoka
  • Publication number: 20150340965
    Abstract: A semiconductor device is provided that can prevent a current from being concentrated into a specific chip, and can reduce loss as well as noise. The semiconductor device according to the present invention includes: a switching element; a main diode that is connected in parallel to the switching element; and an auxiliary diode that is connected in parallel to the switching element and has a different structure from that of the main diode, wherein in a conductive state a current flowing through the auxiliary diode is smaller than that through the main diode, and in a transition period from the conductive state to a non-conductive state a current flowing through the auxiliary diode is larger than that through the main diode.
    Type: Application
    Filed: May 22, 2015
    Publication date: November 26, 2015
    Inventors: Takashi HIRAO, Mutsuhiro MORI
  • Publication number: 20150194479
    Abstract: There is provided a semiconductor device including corundum crystal films of good quality. There is provided a semiconductor device including a base substrate, a semiconductor layer, and an insulating film each having a corundum crystal structure. Materials having a corundum crystal structure include many types of oxide films capable of functioning as an insulating film. Since all the base substrate, the semiconductor layer, and the insulating film have a corundum crystal structure, it is possible to achieve a semiconductor layer and an insulating film of good quality on the base substrate.
    Type: Application
    Filed: September 24, 2013
    Publication date: July 9, 2015
    Applicant: FLOSFIA INC.
    Inventors: Kentaro Kaneko, Toshimi Hitora, Takashi Hirao
  • Publication number: 20150074335
    Abstract: According to one embodiment, a memory system includes non-volatile memory, a block management table that stores whether data in the non-volatile memory is valid or invalid in a unit of cluster, and a controller configured to execute compaction. In the block management table, first information related to likelihood that valid data within the block is invalidated is registered for each of the blocks. The controller is configured to select a block to be a target of the compaction based on the first information and use the selected block to execute the compaction.
    Type: Application
    Filed: March 7, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroki MATSUDAIRA, Takashi Hirao, Aurelien Nam Phong Tran
  • Patent number: 8924636
    Abstract: A management information generating method wherein logical and physical block addresses (BAs) of continuous addresses are associated with each other in the BA translation table. When a logical block is constructed, a value is set for a maximum number of allowable defective physical blocks. A logical block having fewer defects than the set number is set usable, and a logical block having more defects than the set number is set unusable. System logical block construction is performed to preferentially select physical blocks from a plane list including a large number of usable blocks to equalize the number of usable blocks in each plane list. It is determined whether the number of free blocks is insufficient on the basis of a first management unit and whether the storage area for the indicated capacity can be reserved on the basis of the management unit different from the first unit.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Hirao, Hirokuni Yano, Aurelien Nam Phong Tran, Mitsunori Tadokoro, Hiroki Matsudaira, Tatsuya Sumiyoshi, Yoshimi Niisato, Kenji Tanaka
  • Patent number: 8901838
    Abstract: The semiconductor device is included in the LED driving circuit (current regulator) of driving the LED array (with series-connected number m×parallel-connected number n), and is formed of a plurality (n pieces) of LED driving devices of controlling a current (constant-current driving) flowing in each string. A vertical semiconductor device, for example, a vertical MOSFET is used as the LED driving device. Both of a main device functioning as a constant-current driving device and a subsidiary device functioning as a circuit-breaking switch during dimming are formed inside a chip of the device, which are formed of the vertical semiconductor devices. In a first surface of the device, each source region of the main device and the subsidiary device is formed so as to be insulated from each other through an isolation region.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: December 2, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Noboru Akiyama, Takayuki Hashimoto, Takashi Hirao, Nobuyoshi Matsuura, Hideo Ishii
  • Patent number: 8825946
    Abstract: According to one embodiment, when a controller writes update data in a second memory to a first memory which is nonvolatile and a difference between a size of a page and a size of the update data is equal to or greater than a size of a cluster, the controller configured to generate write data by adding, to the update data, data which has the size of the cluster, store an update content of management information corresponding to the update data and an update content storage position indicating a storage position of the update content of the management information in the first memory, and write the generated write data to a block in writing of the first memory.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryoichi Kato, Mitsunori Tadokoro, Takashi Hirao
  • Patent number: 8745443
    Abstract: According to one embodiment, a memory system includes a data manager and a data restorer. The data manager multiplexes difference logs by a parallel writing operation and stores them in a second storage area, the difference logs being difference logs indicating difference information before and after update of a management table; and thereafter multiplexes predetermined data as finalizing logs and stores them in the second storage area. The data restorer determines a system status at startup of the memory system, by judging whether irregular power-off occurs or data destruction occurs in the second storage area, based on a data storage state of the difference logs and the finalizing logs stored in the second storage area.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Hirao, Mitsunori Tadokoro, Hirokuni Yano
  • Patent number: 8664716
    Abstract: In a lateral-type power MOSFET, high breakdown voltage is achieved with suppressing to increase a cell pitch, and a feedback capacity and an ON resistance are decreased. An n? type silicon region having a high resistance to be a region of maintaining a breakdown voltage is vertically provided with respect to a main surface of an n+ type silicon substrate, and the n? type silicon region having the high resistance is connected to the n+ type silicon substrate. Also, a conductive substance is filled through an insulating substance inside a trench formed to reach the n+ type silicon substrate from the main surface of the n+ type silicon substrate so as to contact with the n? type silicon region having the high resistance, and the conductive substance is electrically connected to a source electrode.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: March 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Hashimoto, Takashi Hirao, Noboru Akiyama
  • Publication number: 20130246716
    Abstract: According to one embodiment, when a controller writes update data in a second memory to a first memory which is nonvolatile and a difference between a size of a page and a size of the update data is equal to or greater than a size of a cluster, the controller configured to generate write data by adding, to the update data, data which has the size of the cluster, store an update content of management information corresponding to the update data and an update content storage position indicating a storage position of the update content of the management information in the first memory, and write the generated write data to a block in writing of the first memory.
    Type: Application
    Filed: September 14, 2012
    Publication date: September 19, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryoichi KATO, Mitsunori Tadokoro, Takashi Hirao
  • Publication number: 20130232296
    Abstract: A memory system in embodiments includes a nonvolatile semiconductor memory that stores user data, a forward lookup address translation table and a reverse lookup address translation table, and a controller. The controller is configured to determine that the user data stored in the nonvolatile semiconductor memory is valid or invalid based on these two tables. The controller may perform data organizing of selecting data determined valid and rewriting the data in a new block. The controller may perform write processing and rewriting processing to the new block alternately at a predetermined ratio. The controller may determine whether a predetermined condition is satisfied on a basis of addresses included in write requests and write data in the MLC mode when the condition is satisfied and write data in the SLC mode when the condition is not satisfied.
    Type: Application
    Filed: August 30, 2012
    Publication date: September 5, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinji YONEZAWA, Takashi HIRAO, Hirokuni YANO, Mitsunori TADOKORO, Hiroki MATSUDAIRA, Akira SAWAOKA
  • Publication number: 20130227246
    Abstract: A management information generating method wherein logical and physical block addresses (BAs) of continuous addresses are associated with each other in the BA translation table. When a logical block is constructed, an allowable value is set for the number of defective physical blocks. A logical block having fewer defects than the set number is set usable, and a logical block having more defects than the set number is set unusable. System logical block construction is performed to preferentially select physical blocks from a plane list including a large number of usable blocks to equalize the number of usable blocks in each plane list. It is determined whether the number of free blocks is insufficient on the basis of a first management unit and whether the storage area for the indicated capacity can be reserved on the basis of the management unit different from the first unit.
    Type: Application
    Filed: September 11, 2012
    Publication date: August 29, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi HIRAO, Hirokuni YANO, Aurelien Nam Phong TRAN, Mitsunori TADOKORO, Hiroki MATSUDAIRA, Tatsuya SUMIYOSHI, Yoshimi NIISATO, Kenji TANAKA
  • Publication number: 20120287097
    Abstract: The semiconductor device is included in the LED driving circuit (current regulator) of driving the LED array (with series-connected number m×parallel-connected number n), and is formed of a plurality (n pieces) of LED driving devices of controlling a current (constant-current driving) flowing in each string. A vertical semiconductor device, for example, a vertical MOSFET is used as the LED driving device. Both of a main device functioning as a constant-current driving device and a subsidiary device functioning as a circuit-breaking switch during dimming are formed inside a chip of the device, which are formed of the vertical semiconductor devices. In a first surface of the device, each source region of the main device and the subsidiary device is formed so as to be insulated from each other through an isolation region.
    Type: Application
    Filed: July 27, 2012
    Publication date: November 15, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Noboru AKIYAMA, Takayuki HASHIMOTO, Takashi HIRAO, Nobuyoshi MATSUURA, Hideo ISHII
  • Patent number: 8258711
    Abstract: The semiconductor device is included in the LED driving circuit (current regulator) of driving the LED array (with series-connected number m×parallel-connected number n), and is formed of a plurality (n pieces) of LED driving devices of controlling a current (constant-current driving) flowing in each string. A vertical semiconductor device, for example, a vertical MOSFET is used as the LED driving device. Both of a main device functioning as a constant-current driving device and a subsidiary device functioning as a circuit-breaking switch during dimming are formed inside a chip of the device, which are formed of the vertical semiconductor devices. In a first surface of the device, each source region of the main device and the subsidiary device is formed so as to be insulated from each other through an isolation region.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: September 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Noboru Akiyama, Takayuki Hashimoto, Takashi Hirao, Nobuyoshi Matsuura, Hideo Ishii
  • Publication number: 20120159244
    Abstract: According to one embodiment, a memory system includes a data manager and a data restorer. The data manager multiplexes difference logs by a parallel writing operation and stores them in a second storage area, the difference logs being difference logs indicating difference information before and after update of a management table; and thereafter multiplexes predetermined data as finalizing logs and stores them in the second storage area. The data restorer determines a system status at startup of the memory system, by judging whether irregular power-off occurs or data destruction occurs in the second storage area, based on a data storage state of the difference logs and the finalizing logs stored in the second storage area.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 21, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi HIRAO, Mitsunori TADOKORO, Hirokuni YANO
  • Patent number: 8203380
    Abstract: In a semiconductor device, a high-side driver is arranged in a region closer to a periphery of a semiconductor substrate than a high-side switch, and a low-side driver is arranged in a region closer to the periphery of the semiconductor substrate than the low-side switch. By this means, a path from a positive terminal of an input capacitor to a negative terminal of the input capacitor via the high-side switch and the low-side switch is short, a path from a positive terminal of a drive capacitor to a negative terminal of the drive capacitor via the low-side driver is short, and a path from a positive terminal of a boot strap capacitor to a negative terminal of the boot strap capacitor via the high-side driver is short, and therefore, the parasitic inductance can be reduced, and the conversion efficiency can be improved.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: June 19, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Hashimoto, Takashi Hirao, Noboru Akiyama
  • Patent number: 8125206
    Abstract: A power-supply control IC is included in a switching power supply which drives to turn on and off a semiconductor switching device connected to a DC power supply in series to supply a predetermined constant voltage to an external load, and is a semiconductor device including a semiconductor circuit which controls on and off of the semiconductor switching device. When a current flowing through the load is abruptly increased to cause an error voltage to exceed a predetermined first threshold voltage after the end of a PWM on-pulse generated in synchronization with a switching cycle, a second PWM on-pulse is generated within the same switching cycle. Furthermore, in a plurality of switching cycles after the switching cycle in which the second PWM on-pulse is generated, the first threshold voltage for comparison with the error voltage is switched to a second threshold voltage higher than the first threshold voltage.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: February 28, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Noboru Akiyama, Takayuki Hashimoto, Takashi Hirao, Koji Tateno
  • Patent number: 8120345
    Abstract: A semiconductor device for control applied to a constant-voltage power supply device includes a digital-analog converter circuit which outputs a reference voltage corresponding to a value of a first register with taking an output voltage of a reference voltage source as a criterial reference voltage, and generates a control signal for driving a power semiconductor device based on an output voltage of an error amplifier which differentially amplifies a feedback voltage obtained by resistive-dividing on an output voltage of the constant-voltage power supply device and the reference voltage. An analog-digital converter circuit which converts the feedback voltage to a digital value with taking the output voltage of the constant-voltage power supply device as a reference voltage is provided, and based on the output, a value of a first register is corrected so as to offset an effect of an error in voltage dividing ratio of a voltage dividing resistor circuit.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: February 21, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Noboru Akiyama, Takayuki Hashimoto, Takashi Hirao, Koji Tateno, Takuya Ishigaki
  • Publication number: 20120034474
    Abstract: A joined product according to the present invention is a joined product including a cemented carbide sintered compact serving as a first material to be joined and a cBN sintered compact or a diamond sintered compact serving as a second material to be joined. The first material to be joined and the second material to be joined are joined by a joining material that forms a liquid phase at a temperature exceeding 800° C. and lower than 1000° C. and that is placed between the first material to be joined and the second material to be joined. The first material to be joined and the second material to be joined are joined by resistance heating and pressing at a pressure of 0.1 to 200 MPa.
    Type: Application
    Filed: May 26, 2010
    Publication date: February 9, 2012
    Applicants: National Institute of Advanced Industrial Science and Technology, Sumitomo Electric Hardmetal Corp, Sumitomo Electric Industries, Ltd.
    Inventors: Kimihiro Ozaki, Keizo Kobayashi, Hideki Moriguchi, Tomoyuki Ishida, Akihiko Ikegaya, Tomohiro Fukaya, Takashi Hirao, Takeru Nakashima, Mitsuo Nishimura, Akio Fujimura