Patents by Inventor Takashi Hirao

Takashi Hirao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5141885
    Abstract: A method of fabricating a thin film transistor on an insulating substrate such as quartz or glass without defect in the channel region in semiconductor thin layer, or at the boundary between the semiconductor thin layer and gate insulation layer, but with high mobility and high integration. For that purpose, ions produced by the discharge-decomposition of a hydride gas including dopant are accelerated and implanted into the semiconductor thin layer, wherein the protecting insulation layer for protection of the channel region is of a thickness larger than the projected range of the hydrogen ion.
    Type: Grant
    Filed: June 3, 1991
    Date of Patent: August 25, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihisa Yoshida, Masatoshi Kitagawa, Takashi Hirao
  • Patent number: 5070027
    Abstract: A heterostructure diode is produced by a plasma CVD process. A defect caused on a silicon single crystal substrate by plasma deposition during formation of an amorphous semiconductor film leads to a problem of increase in the dark current due to the defect level. This defect is compensated for by active hydrogen contained in the amorphous semiconductor film so as to reduce the dark current. This can be effected by an annealing process conducted after formation of the heterojunction diode. The RF power is set low in the beginning period of formation of the semiconductor film. A radiation detecting apparatus is provided in which a plurality of the heterostructure diodes are integrated on a common substrate.
    Type: Grant
    Filed: February 23, 1990
    Date of Patent: December 3, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshio Mito, Masatoshi Kitagawa, Takashi Hirao, Yoshitake Yasuno, Ryuma Hirano
  • Patent number: 4980339
    Abstract: A superconductor structure of very high performance is realized by forming a crystalline coating on a substrate of semiconductor, etc. and epitaxially depositing a crystalline superconductor film of good quality on this crystalline coating. Especially, CaF.sub.2 crystal and ZrO.sub.2 crystal of CaF.sub.2 crystal structure have latice constants which match well with the substrate such as Si, GaAs, etc. and the superconductor. The crystalline coating may be a perovskite material such as BaTiO.sub.3 when the superconductor is a perovskite material.
    Type: Grant
    Filed: July 25, 1988
    Date of Patent: December 25, 1990
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kentaro Setsune, Takeshi Kamada, Hideaki Adachi, Kiyotaka Wasa, Takashi Hirao, Osamu Yamazaki, Hidetaka Higashino
  • Patent number: 4861729
    Abstract: A method in which in order to dope impurities, with excellent controllability, into a sidewall of a trench formed in a semiconductor substrate, plasma is generated in a gas including the impurities and the semiconductor substrate is disposed in or near the plasma, so that the impurities may be doped into the sidewall of the trench uniformly and at high precision of concentration control; wherein one of a duluted B.sub.2 H.sub.6 gas and diluted AsH.sub.3 gas is chosen as the gas of the plasma, whereby one of B and As as the impurities directly enters the sidewall of the trench without first passing through a film.
    Type: Grant
    Filed: August 24, 1987
    Date of Patent: August 29, 1989
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Genshu Fuse, Takashi Hirao, Takashi Ohzone
  • Patent number: 4859908
    Abstract: A plasma processing apparatus performs various plasma processings of a substrate having a large area in a semiconductor element manufacturing process, by using highly excited plasma generated at a low pressure under the application of RF power and a magnetic field. In this plasma processing apparatus, a gas is introduced into a vacuum chamber to be used as an ion source, RF power is applied to two electrodes having respective surfaces opposite to each other through the gas to thereby generate the plasma in the vacuum chamber, and a magnetic field is applied to the plasma from a magnetic field source arranged at a predetermined position. The intensity of the applied magnetic field is set to be 1.5 times or more the magnetic field intensity which causes electron cyclotron resonance to occur at the frequency f of the applied RF power. Particularly, when the frequency f of the RF power is 13.56 MHz, the magnetic field intensity is selected to be in the range from 25 gausses to 35 gausses.
    Type: Grant
    Filed: September 23, 1987
    Date of Patent: August 22, 1989
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihisa Yoshida, Kentaro Setsune, Takashi Hirao
  • Patent number: 4800174
    Abstract: A method of producing an amorphous silicon semiconductor device makes use of a capacitance-coupled high-frequency glow-discharge semiconductor production apparatus which is equipped with a plurality of glow-discharge chambers each having a high-frequency electrode and a substrate holder opposing each other and means for supplying material gases to the glow-discharge chambers. A reaction of a material gas is effected in a first glow-discharge chamber, so as to form a semiconductor layer having a first conductivity type on a substrate introduced into the first glow-discharge chamber, and, after moving the substrate into a second glow-discharge chamber, a reaction of a material gas different from the material gas used in the first glow-discharge chamber is effected, thereby forming a semiconductor layer having a second conductivity type on the semiconductor layer of the first conductivity type.
    Type: Grant
    Filed: May 18, 1987
    Date of Patent: January 24, 1989
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichiro Ishihara, Masatoshi Kitagawa, Takashi Hirao
  • Patent number: 4770923
    Abstract: An inorganic protection film (12) such as of silicon nitride for protecting humidity-sensitive functional devices (16) on the substrate from water molecules (15) is formed on an organic substrate (11) such as one made of polycarbonate plastic material, with a soft buffer interface film (13) between the substrate and the protection film, and the buffer film releases stress due to the difference of thermal expansion coefficients of the organic substrate and the protection film.
    Type: Grant
    Filed: November 20, 1985
    Date of Patent: September 13, 1988
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyotaka Wasa, Takashi Hirao, Atsuo Nishikawa, Seiji Nishino, Takeo Ohta
  • Patent number: 4624045
    Abstract: A thin film device such as an amorphous thin film solar battery is easily made with high integration by use of metal-diffused regions in the thin film as an electrical connection region across the thickness of the thin film. By use of such metal-diffused regions 24, 24 . . . for connection between transparent stripe shaped electrodes 21', 21'. . . disposed between glass substrate 20 and amorphous silicon thin film 23 and stripe shaped metal electrodes 25, 25 . . . on the top surface of the thin film 23, series connected solar battery cells can be made with a small number of process steps.
    Type: Grant
    Filed: March 27, 1985
    Date of Patent: November 25, 1986
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichiro Ishihara, Takashi Hirao, Koshiro Mori, Masaharu Ono, Masatoshi Kitagawa
  • Patent number: 4492605
    Abstract: A method for making photovoltaic device comprising the steps of moving at least one substrate into a reaction chamber, causing a plasma reaction of raw material gases in said reaction chamber, thereby forming an amorphous silicon layer of a first conductivity type on said substrate, moving said at least one substrate into a next reaction chamber for a next plasma reaction, causing said next plasma reaction of next raw material gases in said reaction chamber, thereby forming a second amorphous silicon layer of a second conductivity type on said layer of the first conductivity type, the improvement being in after finishing said forming of said an amorphous silicon layer of a first conductivity type, changing the gas atmosphere of said reaction chamber into a different atmosphere which is substantially identical and of equal pressure to the next gas atmosphere of said next reaction chamber, and thereafter moving said substrate to said next reaction chamber.
    Type: Grant
    Filed: March 18, 1983
    Date of Patent: January 8, 1985
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shin-ichiro Ishihara, Takashi Hirao, Koshiro Mori, Motonori Mochizuki
  • Patent number: 4185291
    Abstract: A junction-type FET comprising a semiconductor substrate 21 of a first conductivity type, and island region 22 of a second conductivity type which comprises a channel region and is selectively formed in the semiconductor substrate 21, and a buried isolating region 27 which is selected from the group consisting of an intrinsic layer, a low impurity concentration layer of the second conductivity type and a layer of first conductivity type, the buried isolating layer being formed by ion implantation of impurities of the first conductivity type in the island region 22 while keeping the impurity concentration at the surface thereof relatively high, and the buried isolating layer substantially isolating the channel region from the surface.
    Type: Grant
    Filed: June 16, 1978
    Date of Patent: January 22, 1980
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Hirao, Shigetoshi Takayanagi, Takeshi Onuma, Toshio Sugawa, Kaoru Inoue
  • Patent number: 4143388
    Abstract: A MOS type semiconductor device, wherein at least one oblique face is provided on at least a part of a gate electrode which is provided on a principal face of said substrate with a gate insulation film inbetween, and at a specific depth from the oblique face, that is, in parallel with this oblique face, an ion-implanted layer is provided in a manner to obliquely cross the surface of said substrate. In this MOS type semiconductor device the channel is made immediately underneath the surface of the substrate and in the ion-implanted layer, and therefore the channel length is determined by the thickness of the ion-implanted layer. By controlling the thickness of the ion-implanted layer, a short channel length, which is required for improving the operating speed and/or the handling current capability of MOS type semiconductor devices, is obtainable.
    Type: Grant
    Filed: May 17, 1977
    Date of Patent: March 6, 1979
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideya Esaki, Takashi Hirao, Hakuhei Kawakami