Patents by Inventor Takashi Hoshino

Takashi Hoshino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110037998
    Abstract: A facsimile apparatus includes an acquisition unit and a first registration unit. The acquisition unit acquires a transmission source number and a reception number of a facsimile reception document. The first registration unit acquires use restriction information corresponding to the transmission source number and the reception number acquired by the acquisition unit from a first storage unit for storing first correspondence relation information in which use restriction information of documents and transmission source numbers and reception numbers of facsimile communication are associated with each other, and registers second correspondence relation information in which the use restriction information and the facsimile reception document are associated with each other in a second storage unit for storing correspondence relation information between documents and use restriction information.
    Type: Application
    Filed: March 15, 2010
    Publication date: February 17, 2011
    Applicant: FUJI XEROX CO., LTD.
    Inventor: Takashi HOSHINO
  • Patent number: 7750377
    Abstract: A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconductor portion 5, an n+ type source semiconductor portion 7, and a p+ type gate semiconductor portion 8. The n-type drift semiconductor portion 3 is placed on a principal surface of the n+ type drain semiconductor portion 2 and has first to fourth regions 3a to 3d extending in a direction intersecting with the principal surface. The p+ type gate semiconductor portion 4 is placed on the first to third regions 3a to 3c of the n-type drift semiconductor portion 3. The n-type channel semiconductor portion 5 is placed along the p+ type gate semiconductor portion 4 and is electrically connected to the fourth region 3d of the n-type drift semiconductor portion 3.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: July 6, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Hoshino, Shin Harada, Kazuhiro Fujikawa, Satoshi Hatsukawa, Kenichi Hirotsu
  • Publication number: 20100150593
    Abstract: An image forming apparatus includes: an image holder that holds an image; a transfer unit that includes a transfer member being rotationally driven and forming a pressing portion between the transfer member and the image holder, and that presses a recording medium under transportation at the pressing portion so as to transfer the image held by the image holder onto the transported recording medium; and an adjustment unit that adjusts drive torque for the transfer member by changing the drive torque from a first adjustment state to a second adjustment state, either when a leading edge of the recording medium reaches the pressing portion or when a trailing edge of the recording medium leaves the pressing portion.
    Type: Application
    Filed: September 29, 2009
    Publication date: June 17, 2010
    Inventor: Takashi HOSHINO
  • Patent number: 7712180
    Abstract: A wiper blade (18a) has a rubber holder (22) for holding a blade rubber (21). This rubber holder (22) has a connection block (24) coupled to a wiper arm and two sub-holders (25) fixed on both sides of the connection block (24), and the sub-holders (25) each has two rod-shaped spring members (27) curved with curvature radii smaller than that of a front glass and 11 holder pieces (26) fixed to these rod-shaped spring members (27) in a longitudinal direction at a predetermined interval. Further, this rubber holder (22) is formed so that the two sub-holders (25) are coupled to each other via the connection block (24) in the longitudinal direction.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: May 11, 2010
    Assignee: Mitsuba Corporation
    Inventors: Takashi Hoshino, Hiroki Tokunaka, Junichi Sekiguchi
  • Patent number: 7671387
    Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: March 2, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
  • Patent number: 7671388
    Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: March 2, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
  • Publication number: 20090315082
    Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.
    Type: Application
    Filed: September 1, 2009
    Publication date: December 24, 2009
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
  • Patent number: 7634207
    Abstract: The present invention provides an image forming apparatus. The image forming apparatus includes plural image carriers, an endless intermediate transfer belt, plural first transfer members and a second transfer member. The image forming apparatus starts application of the transfer bias sequentially from the first transfer members disposed upstream and continues to apply the transfer bias to two or more of the first transfer members until the recording medium enters a transfer position where the toner images are transferred by the second transfer member.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: December 15, 2009
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Yoko Miyamoto, Takashi Hoshino
  • Patent number: 7499478
    Abstract: An optical disk apparatus uses a laser driver which can measure the frequency of the high-frequency superimposed current of the semiconductor laser simply and accurately. The apparatus includes a semiconductor laser which emits a laser beam onto the optical disk, a laser driver which drives the semiconductor laser with a current, with the high-frequency current being superimposed thereon, and measures the frequency of the high-frequency current, and a main controller which controls the frequency of the high-frequency current produced by the laser driver by using the frequency measured by the laser driver.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: March 3, 2009
    Assignees: Hitachi, Ltd., Hitachi-LG Data Storage, Inc.
    Inventors: Makoto Nihei, Toshimitsu Kaku, Akihiro Asada, Takashi Hoshino
  • Publication number: 20080277696
    Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.
    Type: Application
    Filed: July 24, 2008
    Publication date: November 13, 2008
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
  • Patent number: 7420232
    Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: September 2, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
  • Publication number: 20080205767
    Abstract: The extraction method and apparatus acquire design data that has a hierarchical structure and is converted into raster data corresponding to drawing onto a substrate and extract from the design data a structural element that composes the design data, is repeatedly described in one hierarchical layer, and satisfies at least one of four extraction conditions concerning a size of the structural element, a number of times of repetition of the structural element in a structural element upper than the structural element, a number of lower structural elements composing the structural element, and a depth of the one hierarchical layer in which the structural element exists.
    Type: Application
    Filed: February 13, 2008
    Publication date: August 28, 2008
    Applicant: FUJIFILM Corporation
    Inventors: Takashi Hoshino, Takashi Toyofuku, Yasuyuki Mochizuki, Yukihisa Ozaki
  • Patent number: 7355736
    Abstract: The scanning type printing apparatus prints an image and/or a text on a recording medium in accordance with image data and/or text data while moving on the recording medium. The apparatus includes a moving unit, an image processing unit that, prior to printing, rotates the image and/or the text to be printed based on the image data and/or the text data and/or reverses front and back thereof; and an ejection head that includes at least one nozzle and at least one ink ejection unit that eject ink.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: April 8, 2008
    Assignee: FUJIFILM Corporation
    Inventors: Takashi Hoshino, Toshiya Kojima, Seiichi Inoue
  • Publication number: 20080025744
    Abstract: The present invention provides an image forming apparatus. The image forming apparatus includes plural image carriers, an endless intermediate transfer belt, plural first transfer members and a second transfer member. The image forming apparatus starts application of the transfer bias sequentially from the first transfer members disposed upstream and continues to apply the transfer bias to two or more of the first transfer members until the recording medium enters a transfer position where the toner images are transferred by the second transfer member.
    Type: Application
    Filed: April 17, 2007
    Publication date: January 31, 2008
    Inventors: Yoko Miyamoto, Takashi Hoshino
  • Publication number: 20070278540
    Abstract: A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconductor portion 5, an n+ type source semiconductor portion 7, and a p+ type gate semiconductor portion 8. The n-type drift semiconductor portion 3 is placed on a principal surface of the n+ type drain semiconductor portion 2 and has first to fourth regions 3a to 3d extending in a direction intersecting with the principal surface. The p+ type gate semiconductor portion 4 is placed on the first to third regions 3a to 3c of the n-type drift semiconductor portion 3. The n-type channel semiconductor portion 5 is placed along the p+ type gate semiconductor portion 4 and is electrically connected to the fourth region 3d of the n-type drift semiconductor portion 3.
    Type: Application
    Filed: June 28, 2007
    Publication date: December 6, 2007
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takashi Hoshino, Shin Harada, Kazuhiro Fujikawa, Satoshi Hatsukawa, Kenichi Hirotsu
  • Patent number: 7294080
    Abstract: A rotational drive device includes a drive motor and a drive transmission mechanism that are coupled together via an input coupling. The input coupling includes a coupling body that is coupled and fixed to an output shaft of the drive motor. A vibration damper that projects outward and damps vibration from the drive motor is disposed at an outer peripheral portion of the coupling body.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: November 13, 2007
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Takashi Hoshino
  • Patent number: 7282760
    Abstract: A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconductor portion 5, an n+ type source semiconductor portion 7, and a p+ type gate semiconductor portion 8. The n-type drift semiconductor portion 3 is placed on a principal surface of the n+ type drain semiconductor portion 2 and has first to fourth regions 3a to 3d extending in a direction intersecting with the principal surface. The p+ type gate semiconductor portion 4 is placed on the first to third regions 3a to 3c of the n-type drift semiconductor portion 3. The n-type channel semiconductor portion 5 is placed along the p+ type gate semiconductor portion 4 and is electrically connected to the fourth region 3d of the n-type drift semiconductor portion 3.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: October 16, 2007
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Hoshino, Shin Harada, Kazuhiro Fujikawa, Satoshi Hatsukawa, Kenichi Hirotsu
  • Patent number: 7254862
    Abstract: A holder piece assembly having holder pieces continuously arranged and leaf spring members connecting between each holder piece, and being curved in the longitudinal direction by elastic force of elastic members is provided. The holder piece assembly is mounted on the front edge of a wiper arm through a clip pin. Blade rubber for wiping window glass surface is mounted on the holder piece assembly. The elastic force of the leaf spring members elastically deformed when the blade rubber is allowed to conform with the window glass surface can disperse the pressing force of the wiper arm over the blade rubber longitudinal direction. The dispersed pressing force can be set by changing the connecting angle between each holder piece according to the window glass curvature thereby the wiper blade versatility is improved.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: August 14, 2007
    Assignee: Mitsuba Corporation
    Inventor: Takashi Hoshino
  • Publication number: 20060202238
    Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.
    Type: Application
    Filed: April 11, 2006
    Publication date: September 14, 2006
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
  • Publication number: 20060179597
    Abstract: A wiper blade (18a) has a rubber holder (22) for holding a blade rubber (21). This rubber holder (22) has a connection block (24) coupled to a wiper arm and two sub-holders (25) fixed on both sides of the connection block (24), and the sub-holders (25) each has two rod-shaped spring members (27) curved with curvature radii smaller than that of a front glass and 11 holder pieces (26) fixed to these rod-shaped spring members (27) in a longitudinal direction at a predetermined interval. Further, this rubber holder (22) is formed so that the two sub-holders (25) are coupled to each other via the connection block (24) in the longitudinal direction.
    Type: Application
    Filed: December 16, 2003
    Publication date: August 17, 2006
    Inventors: Takashi Hoshino, Hiroki Tokunaka, Junichi Sekiguchi