Abstract: A delivery pipe includes an outer pipe, an inner pipe, and a noise emission decreasing device. The outer pipe is connected to a plurality of fuel injectors. The inner pipe is disposed in the outer pipe and has an open end through which an interior of the inner pipe communicates with atmosphere. The noise emission decreasing device acts so as to decrease a noise emitted from the inner pipe. The noise emission decreasing device includes a mesh, a porous member, a vibration suppressing member provided to the inner pipe, an elastic tube fitted into the inner pipe, or a wire harness inserted into the inner pipe.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: In a synchronization system adopted in a synchronous-multisystem control apparatus comprising a plurality of systems operating synchronously with each other at a fixed control period, the synchronous-multisystem control apparatus can be operated in a single-system mode in the event of failures occurring simultaneously in some of the systems. The synchronous-multisystem control apparatus employs a plurality of control circuits each provided for one of the systems.

Abstract: An input shaft 10 is connected rotationally with an intermediary shaft 20 through a connecting drive gear GCV, a connecting first idle gear GC1, a connecting second idle gear GC2 and a connecting driven gear GCN. A fourth speed drive gear G4V, which is formed in a one-piece body with a reverse drive gear GRV, is provided rotatably over the input shaft 10, and a third speed drive gear G3V is provided rotatably over the intermediary shaft 20. Both the third speed drive gear G3V and the fourth speed drive gear G4V mesh with a third and fourth speed driven gear G34N, which is provided rotatably over an output shaft 40. Also, a reverse driven gear GRN, which is connected rotationally with the reverse drive gear GRV through a reverse idle gear GRI, is provided rotatably over the output shaft 40.

Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.

Abstract: An apparatus for calculating a normalized correlation coefficient used as a similarity evaluation measure by using image data values of pixels in a template image and image data values of pixels in a subimage, included in a search image, corresponding to the template image, has a memory that stores image data values of pixels in the search image and calculating means that calculate a sum of image data values of pixels in the template image and a sum of image data values of pixels in the first rectangular region in the search image or a sum of squares of image data values of pixels in the template image and a sum of squares of image data values of pixels in the first rectangular region in the search image.

Abstract: A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

Abstract: Consumption power control is provided for a system LSI made of a combination of a plurality of reusable logic circuit modules, i.e., Intellectual Property (IP) cores. Hardware resources such as interfaces and registers for the consumption power control of other IP cores are prepared and controlled by software for the consumption power control of a system LSI. The consumption power can be controlled at an IP core level. A method is provided which facilitates a system LSI designer to enter a consumption power control specification of a system LSI when the system LSI is configured.

Abstract: A phase locked loop (PLL) circuit is provided to operate in a broad band, including two separate loops one of which is for feed-back of an output from an oscillator to the same oscillator through its associative proportional control unit and the other of which is for feed-back of an output of an oscillator to the same oscillator via an integral control unit. The proportional control unit is arranged to control an output frequency of the oscillator and is operable to generate a control signal based on a difference between input and output signals. The integral control unit is arranged to control the phase of an output signal of the oscillator to thereby generate a control signal based on a phase difference between input and output signals.

Abstract: A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

Abstract: An apparatus for calculating a normalized correlation coefficient used as a similarity evaluation measure by using image data values of pixels in a template image and image data values of pixels in a subimage, included in a search image, corresponding to the template image, has a memory that stores image data values of pixels in the search image and calculating means that calculate a sum of image data values of pixels in the template image and a sum of image data values of pixels in the first rectangular region in the search image or a sum of squares of image data values of pixels in the template image and a sum of squares of image data values of pixels in the first rectangular region in the search image.

Abstract: A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

Abstract: An image processing apparatus obtains a sum A of image data values of pixels in a template image, a sum B of squares of image data values of pixels in a template image, a sum C of image data values of pixels in a sub-image to be processed, of a search image, a sum D of squares of image data values of pixels in the sub-image of the template image, further obtains a threshold value F in advance by using the obtained values A, B, C and D, the number P of pixels in the template image, and the preset value E. Moreover, the apparatus obtains a square of each difference between an image data value of each pixel in the sub-image and that of a corresponding pixel in the template image, and performs cumulative addition for each obtained squares. If the result of cumulative addition exceeds the above-mentioned threshold value, the apparatus closes processing evaluation of a similarity between the sub-image and the template image.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Abstract: An input shaft 10 is connected rotationally with an intermediary shaft 20 through a connecting drive gear GCV, a connecting first idle gear GC1, a connecting second idle gear GC2 and a connecting driven gear GCN. A fourth speed drive gear G4V, which is formed in a one-piece body with a reverse drive gear GRV, is provided rotatably over the input shaft 10, and a third speed drive gear G3V is provided rotatably over the intermediary shaft 20. Both the third speed drive gear G3V and the fourth speed drive gear G4V mesh with a third and fourth speed driven gear G34N, which is provided rotatably over an output shaft 40. Also, a reverse driven gear GRN, which is connected rotationally with the reverse drive gear GRV through a reverse idle gear GRI, is provided rotatably over the output shaft 40. Either the third and fourth speed driven gear G34N or the reverse driven gear GRN is connected to the output shaft 40 by a selective clutch CTD.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Abstract: In an information processing apparatus, a user having no knowledge of a designer of an LSI modifies a floorplan of the LSI without deteriorating the performance of the LSI. The designer who designs the LSI uses a circuit designing apparatus to store circuit information including a functions of each of blocks constituting the LSI, a floorplan regarding allocation of the blocks, and evaluation indices which are the know-how of the designer, with being associated with each other. The user uses a floorplan modifying apparatus to modify the floorplan and to evaluate the modified floorplan according to the evaluation indices.