Patents by Inventor Takashi Imoto
Takashi Imoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150170988Abstract: According to one embodiment, a plurality of semiconductor devices is mounted on a wiring substrate. A surface, on which a semiconductor devices of the wiring substrate are mounted, and the plurality of semiconductor devices are sealed by using a sealing resin. The wiring substrate which is sealed is cut and thus separated into semiconductor apparatuses. The semiconductor apparatuses after the separation are heated. A shield layer is formed by metal sputtering over wiring exposed at the edge of the cut wiring substrate and the sealing resin of the semiconductor apparatus, after the heating.Type: ApplicationFiled: September 2, 2014Publication date: June 18, 2015Inventors: Takeshi WATANABE, Takashi IMOTO, Yuusuke TAKANO, Soichi HOMMA, Katsunori SHIBUYA
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Publication number: 20150171060Abstract: In a manufacturing method of a semiconductor device according to an embodiment, a plurality of semiconductor packages each including a semiconductor chip mounted on a wiring board and a sealing resin layer as objects to be processed, and a tray including a plurality of housing parts are prepared. A depressed portion having a non-penetrating shape or a penetrating shape is formed in the housing part. The semiconductor packages are disposed in the plural housing parts respectively. By sputtering a metal material on the semiconductor package housed in the tray, a conductive shield layer is formed.Type: ApplicationFiled: September 10, 2014Publication date: June 18, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki GOTO, Takashi IMOTO, Takeshi WATANABE, Yuusuke TAKANO, Yusuke AKADA, Yuji KARAKANE, Yoshinori OKAYAMA, Akihiko YANAGIDA
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Publication number: 20150171056Abstract: In a manufacturing method of a semiconductor device of an embodiment, a plurality of semiconductor packages, as objects to be processed, each including a semiconductor chip mounted on a wiring board and a sealing resin layer, and a tray including a plurality of housing parts are prepared. The semiconductor packages are respectively disposed in the plurality of housing parts of the tray. A metal material is sputtered on the semiconductor packages disposed in the housing parts, to thereby form a conductive shield layer covering an upper surface and side surfaces of each of the sealing resin layers and at least a part of side surfaces of each of the wiring boards.Type: ApplicationFiled: September 10, 2014Publication date: June 18, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Goto, Takashi Imoto, Takeshi Watanabe, Yuusuke Takano, Yusuke Akada, Yuji Karakane, Yoshinori Okayama, Akihiko Yanagida
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Publication number: 20150171020Abstract: A semiconductor device includes a conductive shield layer that has a first portion covering a surface of a sealing resin layer and a second portion covering side surfaces of the sealing resin layer and side surfaces of the substrate. Portions of wiring layers, including a grounding wire, on or in the substrate have cut planes which are exposed to the side surfaces of the substrate and spread out in a thickness direction of the substrate. A cut plane of the grounding wire is electrically connected to the shield layer. An area of the cut plane of the grounding wire is larger than an area of a cross section of the grounding wire parallel to, and inward of the substrate from, the cut plane of the grounding wire.Type: ApplicationFiled: September 2, 2014Publication date: June 18, 2015Inventors: Katsunori SHIBUYA, Takashi IMOTO, Soichi HOMMA, Takeshi WATANABE, Yuusuke TAKANO
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Publication number: 20150167157Abstract: A semiconductor manufacturing device has an upper cover configured to be arranged above top surface of unshielded semiconductor device which are mounted on a tray placed on a carrier to go through electromagnetic shielding, and a displacement detector configured to detect an abnormality when the upper cover is raised by at least one of the semiconductor device which is brought into contact with a bottom surface of the upper cover.Type: ApplicationFiled: September 10, 2014Publication date: June 18, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsunori Shibuya, Takashi Imoto, Soichi Homma, Takeshi Watanabe, Yuusuke Takano
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Publication number: 20150171021Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a sealing resin layer containing an inorganic filler so as to seal a semiconductor chip, removing a portion of the surface of the sealing resin layer by dry etching such that a portion of the inorganic filler is exposed, and forming a shield layer so as to cover at least the sealing resin layer.Type: ApplicationFiled: September 2, 2014Publication date: June 18, 2015Inventors: Yuusuke TAKANO, Takashi IMOTO, Takeshi WATANABE, Soichi HOMMA, Katsunori SHIBUYA
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Publication number: 20150070046Abstract: According to one embodiment, a semiconductor device includes a wiring board that has a first surface and a second surface opposed to the first surface, a semiconductor chip provided on the first surface, external connection terminals provided on the second surface, a sealing resin layer provided on the first surface, and a conductive shield layer that covers at least a portion of a side surface of the wiring board and the sealing resin layer. The wiring board includes a first ground wire that is electrically connected to the conductive shield layer, and a second ground wire that is electrically connected to the conductive shield layer and is electrically insulated from the first ground wire.Type: ApplicationFiled: September 2, 2014Publication date: March 12, 2015Inventors: Yuusuke TAKANO, Yoshiaki GOTO, Takeshi WATANABE, Takashi IMOTO
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Patent number: 8896111Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip disposed on a circuit board, an adhesive layer fixing the first semiconductor chip to the circuit board, and a second semiconductor chip having an outer shape smaller than that of the first semiconductor chip. At least a part of the second semiconductor chip is embedded in the adhesive layer. The adhesive layer has a thickness in a range of 95 to 150 ?m. The adhesive layer includes a cured product of a thermosetting resin whose thermal time viscosity at a time that the second semiconductor chip is embedded is in a range of 500 to 5000 Pa·s.Type: GrantFiled: March 12, 2013Date of Patent: November 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Akira Tanimoto, Takashi Imoto, Yoriyasu Ando, Masashi Noda, Naoki Iwamasa, Koichi Miyashita, Masatoshi Kawato, Masaji Iwamoto, Jun Tanaka, Yusuke Dohmae
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Publication number: 20140070428Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip disposed on a circuit board, an adhesive layer fixing the first semiconductor chip to the circuit board, and a second semiconductor chip having an outer shape smaller than that of the first semiconductor chip. At least a part of the second semiconductor chip is embedded in the adhesive layer. The adhesive layer has a thickness in a range of 95 to 150 ?m. The adhesive layer includes a cured product of a thermosetting resin whose thermal time viscosity at a time that the second semiconductor chip is embedded is in a range of 500 to 5000 Pa·s.Type: ApplicationFiled: March 12, 2013Publication date: March 13, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Akira TANIMOTO, Takashi Imoto, Yoriyasu Ando, Masashi Noda, Naoki Iwamasa, Koichi Miyashita, Masatoshi Kawato, Masaji Iwamoto, Jun Tanaka, Yusuek Dohmae
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Publication number: 20130062758Abstract: In one embodiment, a semiconductor device has a substrate, a first semiconductor chip, an electrode, a first and second connection member, and a first and second sealing member. The electrode is disposed on the first semiconductor chip and contains Al. The first connection member electrically connects the electrode and the substrate and contains Au or Cu. The first sealing member seals the first semiconductor chip and the first connection member. One or more second semiconductor chips are stacked on the first sealing member. The second sealing member seals the first connection member, the one or more second semiconductor chips, and the one or more second connection members. A ratio of a total weight W1 of Cl ions and Br ions in the first sealing member to a weight W0 of resins of the substrate and the first sealing member is 7.5 ppm or lower.Type: ApplicationFiled: March 16, 2012Publication date: March 14, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Takashi IMOTO, Yoriyasu Ando, Akira Tanimoto, Masaji Iwamoto, Yasuo Takemoto, Hideo Taguchi, Naoto Takebe, Koichi Miyashita, Jun Tanaka, Katsuhiro Ishida, Shogo Watanabe, Yuichi Sano
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Publication number: 20120286411Abstract: According to one embodiment, there is provided a semiconductor device including a wiring board, a semiconductor chip mounted on a first surface of the wiring board, first external electrodes provided on the first surface of the wiring board, second external electrodes provided on a second surface of the wiring board, and a sealing resin layer sealing the semiconductor chip together with the first external electrodes. The sealing resin layer has a recessed portion exposing a part of each of the first external electrodes. The plural semiconductor devices are stacked to form a semiconductor module with a POP structure. In this case, the first external electrodes of the lower-side semiconductor device and the second external electrodes of the upper-side semiconductor device are electrically connected.Type: ApplicationFiled: March 16, 2012Publication date: November 15, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Takeshi Watanabe, Takashi Imoto, Naoto Takebe, Yuuki Kuro, Yusuke Doumae, Katsunori Shibuya, Yoshimune Kodama, Yuji Karakane, Masatoshi Kawato
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Publication number: 20120257242Abstract: An information processing apparatus and method includes determining whether print data is limited in a number of times of printing, determining whether a setting of storing the print data in the information processing apparatus is valid, and stopping transmission of the print data in a case where it is determined that the print data is limited in the number of times of printing and it is determined that the setting is valid.Type: ApplicationFiled: April 2, 2012Publication date: October 11, 2012Applicant: CANON KABUSHIKI KAISHAInventor: Takashi Imoto
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Patent number: 8237295Abstract: According to one embodiment, a semiconductor device includes a first semiconductor element, a first electrode, a ball part, a second electrode, and a wire. The first electrode is electrically connected to the first semiconductor element. The ball part is provided on the first electrode. The wire connects the ball part and the second electrode. A thickness of a turned-back portion at an end of the wire on a side opposite to the second electrode is smaller than a diameter of the wire.Type: GrantFiled: March 21, 2011Date of Patent: August 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yuichi Sano, Takashi Imoto, Naoto Takebe, Katsuhiro Ishida, Tomomi Honda, Yasushi Kumagai
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Publication number: 20120153471Abstract: A semiconductor device according to the present embodiment includes a substrate including wirings. At least one first semiconductor chip is mounted on a first surface of the substrate and is electrically connected to any of the wirings. A first metal ball is provided on the first surface of the substrate and is electrically connected to the first semiconductor chip through any of the wirings. A first resin seals the wirings, the first semiconductor chip, and the first metal ball on the first surface of the substrate. A top of the first metal ball protrudes from a surface of the first resin and is exposed.Type: ApplicationFiled: September 18, 2011Publication date: June 21, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takeshi WATANABE, Yuji Karakane, Takashi Imoto
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Publication number: 20110309502Abstract: According to one embodiment, a semiconductor device includes a first semiconductor element, a first electrode, a ball part, a second electrode, and a wire. The first electrode is electrically connected to the first semiconductor element. The ball part is provided on the first electrode. The wire connects the ball part and the second electrode. A thickness of a turned-back portion at an end of the wire on a side opposite to the second electrode is smaller than a diameter of the wire.Type: ApplicationFiled: March 21, 2011Publication date: December 22, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Yuichi SANO, Takashi Imoto, Naoto Takebe, Katsuhiro Ishida, Tomomi Honda, Yasushi Kumagai
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Publication number: 20110304050Abstract: According to one embodiment, a semiconductor apparatus includes a substrate, a first semiconductor device, a circuit pattern, and a potential unit. The substrate includes a first insulating layer and a second insulating layer stacked with the first insulating layer. The first semiconductor device is provided on a side of the first insulating layer opposite to the second insulating layer side. The circuit pattern is provided between the first insulating layer and the second insulating layer. The potential unit is provided between the first insulating layer and the second insulating layer. The potential unit is connected to ground or a power source.Type: ApplicationFiled: February 22, 2011Publication date: December 15, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takashi IMOTO, Yusuke AKADA, Masaji RI, Tetsuya SATO
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Patent number: 7932605Abstract: There is disclosed a semiconductor device comprising at least one semiconductor element, one chip mounting base being provided at least one first interconnection on one major surface thereof and at least one second interconnection on the other major surface thereof, and the semiconductor element being electrically connected to at least the one first interconnection and mounted on the one major surface, a sealing member being provided on the one major surface of the chip mounting base and covering the semiconductor element and the first interconnection, at least one third interconnection being provided on a surface of the sealing member, and at least one fourth interconnection being provided in the sealing member and the chip mounting base, and electrically connected to the first interconnection, the second interconnection, and the third interconnection.Type: GrantFiled: August 8, 2007Date of Patent: April 26, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Imoto, Chiaki Takubo
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Patent number: 7682692Abstract: A pressure-sensitive adhesive product contains a substrate having formed on at least one surface thereof a pressure-sensitive adhesive layer, wherein the substrate is formed from a styrene-based resin composition and the pressure-sensitive adhesive layer is formed from an acrylic pressure-sensitive adhesive containing an acrylic polymer, a liquid paraffin, and a rosin-based tackifying resin. In the acrylic pressure-sensitive adhesive, the ratio of the liquid paraffin is preferably 6 to 50 parts by weight based on 100 parts by weight of the acrylic polymer and the ratio of the rosin-based tackifying resin is preferably 1 to 30 parts by weight based on 100 parts by weight of the acrylic polymer. The liquid paraffin may have a number-average molecular weight of 300 to 500 and may have a dynamic viscosity at 37.8° C. of 6 to 80 mm2/second.Type: GrantFiled: January 11, 2006Date of Patent: March 23, 2010Assignee: Nitto Denko CorporationInventors: Tsuneyuki Amano, Takashi Imoto
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Patent number: 7608911Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.Type: GrantFiled: June 24, 2008Date of Patent: October 27, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
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Patent number: 7497535Abstract: Information related to ink mounted to a printer that performs printing is acquired, and information for designating a type of ink that has been set to be used in printing by the printer is acquired. Based on the set type of ink and acquired information, it is determined whether or not the printer can print with a type of ink other than the set type of ink to be used. If it is determined that the printing is possible, displaying is executed to have a user confirm the set type of ink.Type: GrantFiled: June 29, 2006Date of Patent: March 3, 2009Assignee: Canon Kabushiki KaishaInventor: Takashi Imoto