Patents by Inventor Takashi Inoue

Takashi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170199090
    Abstract: A load sensor includes: a substrate; a rib on the substrate; and two vertical transistors. Each vertical transistor includes: a gate electrode, a gate insulation film, and a semiconductor thin film on the side surface of the rib; a bottom electrode layer on a bottom of the substrate, on which the rib is not arranged, with contacting the semiconductor thin film; and a top electrode layer on a top of the rib with contacting the semiconductor thin film. Each vertical transistor flows current between the bottom electrode layer and the top electrode layer when a channel region is provided in the semiconductor thin film. Each straight line along normal line directions of the channel regions in the vertical transistors is arranged on a different side surface of the rib from each other, and has a predetermined angle between the straight lines.
    Type: Application
    Filed: August 21, 2015
    Publication date: July 13, 2017
    Inventors: Hiroo ANAN, Takashi INOUE
  • Publication number: 20170166184
    Abstract: During an upshift of an mechanical speed change mechanism, electric power generated by a first motor is reduced by a given electric power, from a start point of an inertia phase, such that an absolute value of the first motor torque is reduced, and an AT input rotational speed becomes more likely to be reduced. Thus, the upshift of the mechanical speed change mechanism is made more likely to proceed, and variation of drive torque is suppressed.
    Type: Application
    Filed: December 1, 2016
    Publication date: June 15, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takaaki TOKURA, Nobufusa KOBAYASHI, Masato YOSHIKAWA, Takashi INOUE
  • Publication number: 20170162683
    Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.
    Type: Application
    Filed: February 21, 2017
    Publication date: June 8, 2017
    Inventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Yasuhiro OKAMOTO, Yoshinao MIURA, Takashi INOUE
  • Publication number: 20170155774
    Abstract: Plural sensors are arranged respectively for plural toner colors, and oscillate to generate and output detection signals with frequencies corresponding to toner densities using oscillator circuits. An analog switch selects one detection signal among the detection signals. A filter decreases amplitude of the selected detection signal. A first signal line transmits the detection signal with the decreased amplitude. A comparator compares the transmitted detection signal with a predetermined threshold value and outputs as the detection signal a signal of which a level is set as a high level or a low level in accordance with the comparison result, and thereby increases amplitude of the detection signal. A receiver-side IC receives the detection signal with the increased amplitude at a predetermined port, determines a frequency of the received detection signal, and determines the toner density on the basis of the determined frequency.
    Type: Application
    Filed: November 22, 2016
    Publication date: June 1, 2017
    Inventor: Takashi Inoue
  • Publication number: 20170149268
    Abstract: A communication device includes a substrate, a magnetic sheet disposed above an upper surface of the substrate, a first coil disposed above an upper surface of the magnetic sheet, a second coil having a portion facing an edge surface of the substrate in a direction parallel with the upper surface of the substrate, and an electronic component disposed on the upper surface of the substrate. The electronic component is configured to generate noise. The magnetic sheet has a portion overlapping the second coil viewing from above. The electronic component is exposed from the magnetic sheet viewing from above. This communication device has a small size and prevents influence of noise generated by the electronic component.
    Type: Application
    Filed: November 11, 2016
    Publication date: May 25, 2017
    Inventors: HIROSHI YAJIMA, TAKASHI INOUE
  • Patent number: 9660045
    Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: May 23, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Inoue, Toshiyuki Takewaki, Tatsuo Nakayama, Yasuhiro Okamoto, Hironobu Miyamoto
  • Patent number: 9658121
    Abstract: A load sensor is constituted by a rib and a vertical transistor including an organic semiconductor film, and a load measurement can be executed based on a change of a gap between a drain electrode and a source electrode which is a channel length of the vertical transistor. Therefore, a change of a current Ids is in a linear relationship to a load applied to the load sensor.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: May 23, 2017
    Assignee: DENSO CORPORATION
    Inventors: Takashi Inoue, Kensuke Hata, Tetsuya Katoh, Kenichi Sakai, Mayumi Uno, Junichi Takeya
  • Publication number: 20170106864
    Abstract: A vehicle control system includes a limiter device, and a setting device to set an upper speed limit on the limiter device, based on speed limit values extracted from image information. The setting device includes a derivation unit to derive a condition to raise display priority for each speed limit value; an obtainment unit to obtain determination information for determining whether the condition is satisfied; a calculation unit to raise the display priority of the speed limit value that corresponds to the condition determined satisfied with the determination information, among the speed limit values extracted from the image information; a display control unit to display the speed limit values in descending order of the display priority; and a setting unit configured to set the upper speed limit on the limiter device, based on one of the displayed speed limit values, selected by an occupant of the vehicle.
    Type: Application
    Filed: September 19, 2016
    Publication date: April 20, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takato MASUDA, Takashi INOUE, Tetsuya TAIRA, Keiji YAMASHITA, Nobuyuki TOMATSU, Sokfan YEE
  • Publication number: 20170103898
    Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.
    Type: Application
    Filed: December 20, 2016
    Publication date: April 13, 2017
    Inventors: Takashi INOUE, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Publication number: 20170090657
    Abstract: Provided is a touch panel having superior impact resistance and good design on an operation face side without a decorative layer. The touch panel is manufactured by providing a cover member on an operation face of the substrate and at an inner side of a lead-out line wiring region so as to avoid lead-out lines of the first electrodes and the second electrodes, and forming a housing portion by insert injection molding using resin material to the step portion created by disposing the cover member, so as to make a front face of the housing portion flush with a front face of the cover member, and so as to sandwich an outer edge of the substrate from upper and lower sides.
    Type: Application
    Filed: September 20, 2016
    Publication date: March 30, 2017
    Inventors: Yasuyuki Naito, Kiyoyuki Deguchi, Takashi Inoue, Tomohiro Ishii, Tsubasa Mitsuhashi
  • Publication number: 20170090656
    Abstract: Provided is a touch panel having superior impact resistance and good design on an operation face side without a decorative layer. The touch panel is manufactured by forming a cut out portion at an outer edge of a substrate on an operation face side of the substrate so as to cover a lead-out line wiring region of lead-out lines of first electrodes and second electrodes, and forming a housing portion by insert injection molding using resin material so as to sandwich the outer edge of the substrate from upper and lower sides with an operation region of a sensor unit being a front face side, and such that the cut out portion is covered and a front face of the housing portion is arranged flush with the operation face of the substrate.
    Type: Application
    Filed: September 20, 2016
    Publication date: March 30, 2017
    Inventors: Yasuyuki Naito, Kiyoyuki Deguchi, Takashi Inoue, Tsubasa Mitsuhashi
  • Patent number: 9601609
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a potential fixing layer, a channel underlayer, a channel layer, and a barrier layer formed above a substrate, a trench that penetrates the barrier layer and reaches as far as a middle of the channel layer, a gate electrode disposed by way of an insulation film in the trench, and a source electrode and a drain electrode formed respectively over the barrier layer on both sides of the gate electrode. A coupling portion inside the through hole that reaches as far as the potential fixing layer electrically couples the potential fixing layer and the source electrode. This can reduce fluctuation of the characteristics such as a threshold voltage and an on-resistance.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: March 21, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
  • Patent number: 9594245
    Abstract: An adaptive optics system includes a spatial light modulator configured to spatially modulate a phase of an optical image incident on a modulation surface and a wavefront sensor including a lens array having a plurality of two-dimensionally arranged lenses and an optical detection element for detecting a light intensity distribution including converging spots formed by the lens array and configured to receive the optical image after the modulation from the spatial light modulator, and compensates for wavefront distribution by controlling a phase pattern displayed in the spatial light modulator based on a wavefront shape of the optical image obtained from the light intensity distribution, wherein a correspondence relation between the modulation surface and the wavefront sensor is adjusted.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: March 14, 2017
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Hongxin Huang, Takashi Inoue
  • Publication number: 20170054014
    Abstract: The semiconductor device includes a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.
    Type: Application
    Filed: November 8, 2016
    Publication date: February 23, 2017
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
  • Publication number: 20170031158
    Abstract: In an aberration-correcting method according to an embodiment of the present invention, in an aberration-correcting method for a laser irradiation device 1 which focuses a laser beam on the inside of a transparent medium 60, aberration of a laser beam is corrected so that a focal point of the laser beam is positioned within a range of aberration occurring inside the medium. This aberration range is not less than n×d and not more than n×d+?s from an incidence plane of the medium 60, provided that the refractive index of the medium 60 is defined as n, a depth from an incidence plane of the medium 60 to the focus of the lens 50 is defined as d, and aberration caused by the medium 60 is defined as ?s.
    Type: Application
    Filed: October 11, 2016
    Publication date: February 2, 2017
    Inventors: Haruyasu ITO, Naoya MATSUMOTO, Takashi INOUE
  • Publication number: 20170030776
    Abstract: A waveform measurement device includes an input spectrum acquisition unit for acquiring an input intensity spectrum being an intensity spectrum of pulsed light, an optical element inputting the pulsed light and outputting light having an intensity spectrum corresponding to a phase spectrum of the pulsed light, an output spectrum acquisition unit for acquiring an output intensity spectrum being an intensity spectrum of the light output from the optical element, and a phase spectrum determination unit for determining the phase spectrum of the pulsed light by comparing an output intensity spectrum calculated when the pulsed light having an input intensity spectrum and a virtual phase spectrum is assumed to be input to the optical element with the output intensity spectrum acquired in the output spectrum acquisition unit. The phase spectrum determination unit sets the virtual phase spectrum by deforming the control phase spectrum.
    Type: Application
    Filed: April 8, 2015
    Publication date: February 2, 2017
    Inventors: Takashi INOUE, Koyo WATANABE, Koji TAKAHASHI, Naoya MATSUMOTO
  • Patent number: 9559183
    Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Publication number: 20170005189
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a third semiconductor layer formed over the second semiconductor layer, a gate electrode formed over the third semiconductor layer, and a gate insulating film formed between the third semiconductor layer and the gate electrode. The second semiconductor layer includes an Aly?1-yN layer (? includes Ga or In, and 0?y<1), and the third semiconductor layer includes an Alz?1-zN layer (0?z<1). y of the Aly?1-yN layer forming the second semiconductor layer increases from the third semiconductor layer to the first semiconductor layer at least in a region under the gate electrode. There is a relationship “z>y” at an interface between the second nitride semiconductor layer and the third nitride semiconductor layer.
    Type: Application
    Filed: September 14, 2016
    Publication date: January 5, 2017
    Inventors: Yasuhiro OKAMOTO, Tatsuo NAKAYAMA, Takashi INOUE, Hironobu MIYAMOTO
  • Patent number: 9536978
    Abstract: To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: January 3, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Ryohei Nega, Masaaki Kanazawa, Takashi Inoue
  • Patent number: D783020
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: April 4, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Takashi Inoue