Patents by Inventor Takashi Kumagai

Takashi Kumagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090298403
    Abstract: A dust box includes: an attachment portion configured to be attached to a dust-discharging nozzle extending from a housing of an electric tool; and a dust-collecting portion connected to the attachment portion and configured to store dust particles to be discharged from the nozzle. The dust-collecting portion mainly consists of a box which is made of synthetic resin and configured to be detachably connected to the attachment portion, and a paper bag received in the box and configured to store the dust particles to be discharged from the nozzle.
    Type: Application
    Filed: April 27, 2009
    Publication date: December 3, 2009
    Applicant: MAKITA CORPORATION
    Inventors: Yukio Yamashiro, Hirokazu Hagiwara, Yoshifumi Morita, Takashi Kumagai
  • Patent number: 7616520
    Abstract: An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, wherein the display memory includes a plurality of RAM blocks each of which includes first and second RAM block regions; wherein each of the RAM blocks includes a wordline control circuit which controls a plurality of wordlines provided in each of the first and second RAM block regions; wherein the wordline control circuit is disposed between the first and second RAM block regions; wherein the first and second RAM block regions are disposed along a first direction; and wherein the wordlines extend along the first direction.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: November 10, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Satoru Kodaira, Noboru Itomi, Shuji Kawaguchi, Takashi Kumagai, Junichi Karasawa, Satoru Ito
  • Patent number: 7613066
    Abstract: In an integrated circuit device, a data line driver block which drives data lines of a display panel based on data supplied from a RAM block from which data is read N times (N is an integer larger than one) in one horizontal scan period 1H of the display panel includes first to N-th divided data line driver blocks disposed along a first direction in which bitlines extend. When data supplied from the RAM block is M bits (M is an integer larger than 1) and grayscale of a pixel corresponding to the data line is G bits, each of the first to N-th divided data line driver blocks includes (M/G) (multiple of three) data line driver cells which drive (M/G) data lines. (M/3G) R data line driver cells are provided in a first subdivided driver, (M/3G) G data line driver cells are provided in a second subdivided driver, and (M/3G) B data line driver cells are provided in a third subdivided driver.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: November 3, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Satoru Kodaira, Noboru Itomi, Shuji Kawaguchi, Takashi Kumagai, Junichi Karasawa, Satoru Ito, Masahiko Moriguchi, Kazuhiro Maekawa
  • Patent number: 7593270
    Abstract: An integrated circuit device has a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines. The display memory includes a plurality of RAM blocks, each of the RAM blocks including a plurality of wordlines WL, a plurality of bitlines BL, a plurality of memory cells MC, and a data read control circuit. Each of the RAM blocks is disposed along a first direction X in which the bitlines BL extend. The data read control circuit controls data reading so that data for pixels corresponding to the signal lines is read out by N times reading in one horizontal scan period 1H of the display panel (N is an integer larger than 1).
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: September 22, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Satoru Kodaira, Noboru Itomi, Shuji Kawaguchi, Takashi Kumagai, Junichi Karasawa, Satoru Ito
  • Publication number: 20090196293
    Abstract: The present invention relates to a packet transfer unit, which comprises a search key memory that stores a search key for a transfer destination of a packet and verification information generated from the search key, in association with a storage location of transfer information memorized in a transfer information memory, wherein a transfer information acquisition unit searches the search key memory by using the search key generated based on the header information and the verification information generated from the search key, acquires storage location information of the transfer information from the search key memory when a match with the search key and the verification information memorized in the search key memory is found, and acquires the transfer information stored in the transfer information memory based on the acquired storage location information, and wherein a transfer unit transfers the packet based on the acquired transfer information.
    Type: Application
    Filed: April 6, 2009
    Publication date: August 6, 2009
    Inventors: Tatsuo Kanetake, Kazuo Sugai, Takashi Kumagai
  • Patent number: 7567479
    Abstract: An integrated circuit device includes: first to Nth circuit blocks CB1 to CBN disposed along a direction D1, the circuit blocks CB1 to CBN includes a data driver block DB. A data driver DR included in the data driver block DB includes Q driver cells DRC1 to DRCQ arranged along a direction D2, each of the driver cells outputting a data signal corresponding to image data for one pixel. When a width of each of the driver cells DRC1 to DRCQ in the direction D2 is WD, each of the circuit blocks CB1 to CBN has a width WB in the direction D2 of “Q×WD?WB<(Q+1)×WD”.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: July 28, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru Ito, Takashi Fujise, Junichi Karasawa, Satoru Kodaira
  • Patent number: 7564734
    Abstract: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN disposed along a direction D1, a first interface region provided on the D2 side of the circuit blocks CB1 to CBN, and a second interface region provided on the D4 side of the circuit blocks CB1 to CBN. The circuit blocks CB1 to CBN include a data driver block DB and a circuit block other than the data driver block DB. When the widths of the first interface region, the circuit blocks CB1 to CBN, and the second interface region in the direction D2 are respectively W1, WB, and W2, the integrated circuit device has a width W in the direction D2 of “W1+WB+W2?W<W1+2×WB+W2”.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: July 21, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru Ito, Takashi Fujise, Junichi Karasawa, Satoru Kodaira
  • Patent number: 7561478
    Abstract: An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a logic circuit block LB, a grayscale voltage generation circuit block GB, data driver blocks DB1 to DB4, and a power supply circuit block PB. The data driver blocks DB1 to DB4 are disposed between the logic circuit block LB and the grayscale voltage generation circuit block GB, and the power supply circuit block PB.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: July 14, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru Ito, Takashi Fujise, Junichi Karasawa, Satoru Kodaira, Katsuhiko Maki
  • Patent number: 7532419
    Abstract: High-rate writing of data recorded on a CD into a hard disk drive (HDD) is performed while reproducing data read out of the CD at the standard bit rate prescribed for the CD. PCM data corresponding to a playback time of 10 seconds, for example, is read out of a CD and stored in a memory. The data is read out of the memory at appropriate timing and outputted after being converted into an analog audio signal by a D/A converter. In parallel, data for writing is read out of the CD in succession to reading of the data for playback and stored in the memory. The data read out of the memory is coded and compressed by an encoder and then stored in the memory. The compressed data is read out of the memory in units of a certain amount suitable for writing in an HDD and then written in the HDD.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: May 12, 2009
    Assignee: Sony Corporation
    Inventors: Toshiyuki Arai, Takashi Kumagai, Hajime Inai, Hiroaki Sato, Fumitake Yodo, Masami Oyama
  • Patent number: 7522441
    Abstract: An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a high-speed interface circuit block HB which transfers data through a serial bus using differential signals, and a circuit block other than HB. The high-speed interface circuit block HB is disposed as an Mth circuit block CBM (2?M?N?1) of the circuit blocks CB1 to CBN.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: April 21, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru Ito, Takashi Fujise, Junichi Karasawa, Satoru Kodaira
  • Patent number: 7522592
    Abstract: The present invention relates to a packet transfer unit, which comprises a search key memory that stores a search key for a transfer destination of a packet and verification information generated from the search key, in association with a storage location of transfer information memorized in a transfer information memory, wherein a transfer information acquisition unit searches the search key memory by using the search key generated based on the header information and the verification information generated from the search key, acquires storage location information of the transfer information from the search key memory when a match with the search key and the verification information memorized in the search key memory is found, and acquires the transfer information stored in the transfer information memory based on the acquired storage location information, and wherein a transfer unit transfers the packet based on the acquired transfer information.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: April 21, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Tatsuo Kanetake, Kazuo Sugai, Takashi Kumagai
  • Publication number: 20090091580
    Abstract: An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and the wordline control circuit selecting an identical wordline N times (N is an integer larger than one) from among the wordlines in one horizontal scan period of the display panel.
    Type: Application
    Filed: December 2, 2008
    Publication date: April 9, 2009
    Applicant: Seiko Epson Corporation
    Inventors: Satoru Kodaira, Noboru Itomi, Shuji Kawaguchi, Takashi Kumagai, Junichi Karasawa, Satoru Ito
  • Patent number: 7495988
    Abstract: An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects VSSL for supplying a first power supply voltage VSS to memory cells MC are formed in a metal interconnect layer in which a plurality of wordlines WL are formed; and wherein a plurality of second power supply interconnects VDDL for supplying a second power supply voltage VDD to the memory cells are formed in another metal interconnect layer in which a plurality of bitlines BL are formed, the second power supply voltage VDD being higher than the first power supply voltage VSS. A plurality of bitline protection interconnects SHD are formed in a layer above the bitlines BL, and each of the bitline protection interconnects SHD at least partially covers one of the bitlines BL in a plan view.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: February 24, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Satoru Kodaira, Noboru Itomi, Shuji Kawaguchi, Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa
  • Patent number: 7492659
    Abstract: An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects for supplying a first power supply voltage to a plurality of memory cells are provided in a metal interconnect layer in which a plurality of bitlines are formed; wherein a second power supply interconnect for supplying a second power supply voltage to the memory cells is provided in a metal interconnect layer in which a plurality of wordlines are formed, the second power supply voltage being higher than the first power supply voltage; wherein a plurality of bitline protection interconnects are formed in a layer above the bitlines, each of the bitline protection interconnects at least partially covering one of the bitlines in a plan view; and wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory is provided in a layer above the bitline protection interconnects, the third power supply voltage being
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: February 17, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Satoru Kodaira, Noboru Itomi, Shuji Kawaguchi, Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa
  • Patent number: 7471573
    Abstract: An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and the wordline control circuit selecting an identical wordline N times (N is an integer larger than one) from among the wordlines in one horizontal scan period of the display panel.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: December 30, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Satoru Kodaira, Noboru Itomi, Shuji Kawaguchi, Takashi Kumagai, Junichi Karasawa, Satoru Ito
  • Publication number: 20080192519
    Abstract: In a power conversion apparatus that boosts a solar light voltage, converts it to AC and supplies AC power to a load or system, power loss is reduced and efficiency is improved. An inverter unit, in which AC sides of three single-phase inverters receive DC power from respective sources with a voltage ratio of 1:3:9 as respective inputs are connected in series. Gradational output voltage control of an output voltage is carried out using the sum of the respective generated AC voltages. Also, a solar light voltage is boosted by a chopper circuit to generate the highest voltage DC power source. When the solar light voltage exceeds a predetermined voltage, the boosting of the chopper circuit is stopped, thereby reducing power loss due to the boosting.
    Type: Application
    Filed: February 21, 2006
    Publication date: August 14, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akihiko Iwata, Makoto Seto, Masaki Yamada, Shigeki Harada, Noriyuki Matsubara, Takashi Kumagai
  • Patent number: 7411861
    Abstract: An integrated circuit device includes a RAM block including a plurality of wordlines WL, a plurality of bitlines BL, a plurality of memory cells MC, wordline control circuit, and a data read control circuit, and a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block. The data read control circuit reads data for pixels corresponding to the signal lines by N (N is an integer larger than one) times reading in one horizontal scan period 1 H of the display panel. The data line driver block includes first to N-th divided data line driver blocks, each of which drives a different data line group of the data line groups and is disposed along a first direction X in which the bitlines BL extend.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: August 12, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Satoru Kodaira, Noboru Itomi, Shuji Kawaguchi, Takashi Kumagai, Junichi Karasawa, Satoru Ito
  • Patent number: 7411804
    Abstract: An integrated circuit device, including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines; and the memory block MB includes a memory cell array, a row address decoder RD, and a sense amplifier block SAB.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: August 12, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru Ito, Takashi Fujise, Junichi Karasawa, Satoru Kodaira
  • Patent number: 7391668
    Abstract: An integrated circuit device, a first direction being a direction extending from a first side which is a shorter side of the integrated circuit device to a third side opposed to the first side, a second direction being a direction extending from a second side which is a longer side of the integrated circuit device to a fourth side opposed to the second side, includes: a first to a Nth circuit blocks (N is an integer more than 2) arranged in the first direction. One of the first to the Nth circuit blocks is a programmable ROM block in which at least a part of data programmed is stored by a user; the programmable ROM block includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines; and the plurality of word lines extend in the second direction.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: June 24, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Kanji Natori, Kimihiro Maemura, Takashi Kumagai
  • Patent number: 7388803
    Abstract: An integrated circuit device includes: a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block. The data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups. The wordline control circuit drives an identical wordline N times from among the wordlines in one horizontal scan period of the display panel. The first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: June 17, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Satoru Kodaira, Noboru Itomi, Shuji Kawaguchi, Takashi Kumagai, Junichi Karasawa, Satoru Ito