Abstract: Lighting apparatus 100 lights a light source 2 of a headlamp, and includes: a connection terminal 113 to which a abnormality notification apparatus 200 is connected; a notification signal output unit for outputting a notification signal relating to a condition of the light source 2 and/or a condition of the light source lighting apparatus 100 to the abnormality notification apparatus 200 via the connection terminal 113; and a communication signal output unit for outputting a communication signal having a different signal form to the notification signal to an external communication apparatus 300, from the connection terminal 113. Therefore the notification of an abnormality relating to the light source 2 and/or the light source lighting apparatus 100 and the communication with an external communication apparatus 300 can be performed using a single connection terminal 113.

Abstract: A light emitting diode apparatus that includes a single DC/DC converter section that has two circuits connected in parallel: a flyback type boosting circuit and a boosting circuit. The former includes a transformer and a switching device and the like to boost DC voltage of a DC power supply, and the latter includes a transformer and a switching device and the like to do likewise. A control section carries out switching control of the switching devices and in such a manner that shifts from each other the phases of current Ida and current Idb to be supplied from the two boosting circuits and to a plurality of LED and the like connected in series in a light emitting section.

Abstract: Problem to be Solved: In left and right independent lighting power sources, even when left and right light-emitting units each including one or a plurality of LEDs light up with a time difference, the quality of emission as headlamps is increased by making it difficult to visually identify the time difference. Solution: A DC/DC converter for supplying the electric power supplied by a battery to the light-emitting unit is operated to change the current supplied to the light-emitting unit such that the current is gradually increased to attain a rated current, to thus avoid the case where one of the left and right headlamps enters a lighting state, when the other does not light up yet.

Abstract: When a current which is conducted from a direct current power supply 8 to a choke coil L1 after a switching transistor 7 is turned on has a predetermined value, an LED lighting device lights up an LED series circuit by conducting a pulse-shaped current which occurs by turning off the switching transistor 7 to the LED series circuit. A cycle period at which the pulse-shaped current is generated is determined according to the average value of the current flowing through the LED series circuit by using an oscillator (VCO) 4. The LED lighting device controls each of the pulse-shaped current value and the average current value arbitrarily.

Abstract: A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.

Abstract: A memory includes memory cells, wherein during a first write operation in which first logical data is written in all memory cells connected to a first word line, a source line driver and a word line driver, the source line driver shifts a voltage of a selected source line corresponding to the first word line in a direction away from the voltage of the first word line and the word line driver shifts a voltage of a second word line in a same direction as a transition direction of voltage of a selected source line, and during a second write operation in which second logical data is written in a selected cell connected to the first word line, the source line driver and the word line driver shift voltages of the selected source line and the second word line in a direction approaching the voltage of the first word line.

Abstract: A discharge lamp ballast apparatus includes an F/F 10 for maintaining the on or off operation of a high-side switching device Q1 of an inverter in synchronization with a rising edge and falling edge of a main signal, and a return unit 9 for generating a signal for returning, even if the output Q of the F/F is inverted owing an unforeseen situation, the output to the polarity to be output normally; and returns the output of the F/F 10 to the first polarity to be output normally using the return signal.

Abstract: This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically floating state; an emitter layer contacting with the source layer, the emitter layer having an opposite conductive type to the source layer; a word line including the source layer, the drain layer, and the body, the word line being provided to memory cells arrayed in a first direction in a plurality of tow-dimensionally arranged memory cells; a source line connected to the source layers of the memory cells arrayed in the first direction; and a bit line connected to the drain layers of the memory cells arrayed in a second direction intersecting the first direction.

Abstract: A capacitor 42 (C1) of a first bootstrap circuit 4 for maintaining the ON state of a first switching device 61, one of the two switching devices disposed on a higher potential side of first DC voltage V1, is not only charged with second DC voltage V2, but also supplied with a charging current from third DC voltage V3 on a secondary winding n2 side of a transformer 22, and maintains the ON state of the first switching device 61 for a long time with the charge of both of them. This makes it possible to fix the polarity of the voltage to be applied to the discharge lamp 8 to the single side polarity closer to the DC output operation.

Abstract: This disclosure concerns a method of driving a memory including memory cells, bit lines, and word lines, each memory cell having a source, a drain, and a floating body, the method comprising performing a refresh operation for recovering deterioration of first logical data of the memory cells and deterioration of second logical data of the memory cells, wherein in the refresh operation, the number of the carriers injected into the floating body is larger than the number of the carriers discharged from the floating body when a potential at the floating body is larger than a critical value, and the number of the carriers injected into the floating body is smaller than the number of the carriers discharged from the floating body when the potential at the floating body is smaller than the critical value.

Abstract: A memory includes: first sense amplifiers arranged in a first interval of an arrangement of memory cell arrays, each being connected to first bit lines corresponding to two memory cell arrays provided at both sides of the first sense amplifier; second sense amplifiers arranged in a second interval of the arrangement of the memory cell arrays, each being connected to second bit lines corresponding to two memory cell arrays at both sides of the second sense amplifier; edge arrays provided beside both ends of an arrangement of the memory cell arrays, the edge arrays generating only the reference data; and edge sense amplifiers provided between the arrangement of the memory cell arrays and the edge arrays, wherein the edge sense amplifier detects data from the memory cell array at one end of the memory cell arrays based on the reference data from one of the edge arrays.

Abstract: A semiconductor memory device includes: a semiconductor layer formed on an insulating layer; a plurality of transistors formed on the semiconductor layer and arranged in a matrix form, each of the transistors having a gate electrode, a source region and a drain region, the electrodes in one direction constituting word lines; source contact plugs connected to the source regions of the transistors; drain contact plugs connected to the drain regions of the transistors; source wirings each of which commonly connects the source contact plugs, the source wirings being parallel to the word lines; and bit lines formed so as to cross the word lines and connected to the drain regions of the transistors via the drain contact plugs. Each of the transistors has a first data state having a first threshold voltage and a second data state having a second threshold voltage.

Abstract: This disclosure concerns a memory including a memory cell including a drain, a source and a floating body, wherein when a refresh operation is executed, a first current is carried from the drain or the source to the body and a second current is carried from the body to the second gate electrode by applying a first voltage and a second voltage to the first gate electrode and the second gate electrode, the first voltage and the second voltage being opposite in polarity to each other, and a state of the memory cell is covered to an stationary state in which an amount of the electric charges based on the first current flowing in one cycle of the refresh operation is almost equal to an amount of the electric charges based on the second current flowing in one cycle of the refresh operation.

Abstract: A vehicle headlamp includes a light source section 1 for emitting light accompanied by heat; a heat pipe 3 thermally connected with the light source section for absorbing and transferring the heat generated by the light source section; a heat radiating member 4 furnished in a position away from the optical axis of the light generated by the light source section and closer to the front than the light source section to be thermally connected to the heat pipe, for radiating the heat transmitted by the heat pipe to produce a convection current; and a headlamp case 6 housing light source section, the heat pipe, and the heat radiating member such that a part of the front lens for transmitting the light from the light source section is formed above the heat radiating material.

Abstract: A memory including; cells, wherein a refresh operation includes a first refresh and a second refresh, in the first refresh, a first potential higher than a gate potential in a retention is applied to the gate in a state having a source potential applied to the drain, and thereafter the gate potential in the retention is applied to the gate, thereby a first current passes to the cell, and in the second refresh, a second potential higher than a gate potential in the retention is applied to the gate, and a third potential higher than the gate potential in the retention is applied to the drain, thereby a second current passes to the cell, and a state of the cell is shifted to an equilibrium state in which amounts of the first and the second currents flowing during one cycle becomes substantially equal.

Abstract: This disclosure concerns a semiconductor memory device comprising: a memory cell array having memory cells arrayed two-dimensionally; word lines connected to the memory cells of rows of the memory cell array; bit lines connected to the memory cells of columns of the memory cell array; sense amplifiers connected to the bit lines, and detecting data stored in the memory cells; a test pad passing a predetermined reference current from a power source, and transmitting a reference voltage based on the reference current; and test circuits connected between the power source and the test pad and intervening between the power source and the bit lines, the test circuits passing test currents according to the reference voltage via the bit lines.

Abstract: This disclosure concerns a semiconductor memory device comprising memory cells including floating bodies and storing therein logic data; bit lines and word lines connected to the memory cells; sense amplifiers connected to the bit lines; a refresh controller instructing a refresh operation for restoring deteriorated storage states of the memory cells; and a refresh interval timer setting a refresh interval between one refresh operation and a next refresh operation to a first interval in a data read mode or a data write mode, and setting the refresh interval to a second interval longer than the first interval in a data retention mode, the data read mode being a mode in which the data stored in the selected memory cell is read to an outside of the device, the data write mode being a mode in which data from the outside is written to the selected memory cell.

Abstract: A history management apparatus includes: a storage unit that stores history information of image processing which contains set-membership information containing pieces of document identification information of an input document and an output document, and an image of at least one of the input document and the output document as history information; and a notification unit that, when history information in which a surveillance target element is contained in an image of an input document or an image of an output document is detected from the storage unit, notifies a notified party of such as the detected history information. When the surveillance target element is not contained in both of the images in the history information, and it is identified that at least one of ancestral documents of the input document has the surveillance target element, the notification unit notifies the notified party of the history information.

Abstract: A memory includes a first and a second bit lines (BL); a first and a second sense nodes (SN); a first transfer gate between the 1st-BL and the 1st-SN; a second transfer gate (TG) between the 2nd-BL and the 2nd-SN; a latch circuit latching data to the 1st and 2nd-SN; a first data line (DQ) from the 1st-SN to outside; and a 2nd-DQ from the 2nd-SN to outside, wherein write data is transmitted from the 1st and 2nd-DQ to the 1st and 2nd-SN corresponding to selected cells before the 1st and 2nd-TG are set to be a conductive state, when writing data into the selected cells to be written out of the cells, and write data in the 1st and 2nd-SN corresponding to the selected cells are started to be written into the selected cells, when the 1st and 2nd-TG are set to be a conductive state.

Abstract: Equipment for vehicle in accordance with the present invention includes: a vehicle-mounted unit which runs with respect to a vehicle body ground on a side of a negative electrode of a battery; an impedance component having an end connected to the vehicle body ground, and another end connected to a circuit ground; a circuit to be controlled which runs with respect to the circuit ground; a control unit which runs with respect to the circuit ground, for controlling the circuit to be controlled and for outputting a communication signal in a digital form which is to be transmitted to the vehicle-mounted unit; and a communication interface circuit which runs with respect to both the vehicle body ground and the circuit ground, for cancelling a potential difference between the vehicle body ground and the circuit ground, and for carrying out bidirectional communications between the vehicle-mounted unit and the control unit.