Abstract: This disclosure concerns a semiconductor memory device including Fin semiconductors extending in a first direction; source layers provided in the Fin semiconductors; drain layers provided in the Fin semiconductors; floating bodies provided in the Fin semiconductors between the source layers and the drain layers, the floating bodies being in an electrically floating state and accumulating or discharging carries so as to store data; first gate electrodes provided in first grooves located between the Fin semiconductors adjacent to each other; second gate electrodes provided in second grooves adjacent to the first grooves and located between the Fin semiconductors adjacent to each other; bit lines connected to the drain layers, and extending in a first direction; word lines connected to the first gate electrodes, and extending in a second direction orthogonal to the first direction; and source lines connected to the source layers, and extending in the second direction.

Abstract: A DC/DC converter device according to the present invention includes a plurality of resonant DC/DC converters connected in parallel, and a timing control circuit driving the plurality of resonant DC/DC converters at substantially the same frequency with a phase shift.

Abstract: A semiconductor memory device includes: a semiconductor layer formed on an insulating layer; a plurality of transistors formed on the semiconductor layer and arranged in a matrix form, each of the transistors having a gate electrode, a source region and a drain region, the electrodes in one direction constituting word lines; source contact plugs connected to the source regions of the transistors; drain contact plugs connected to the drain regions of the transistors; source wirings each of which commonly connects the source contact plugs, the source wirings being parallel to the word lines; and bit lines formed so as to cross the word lines and connected to the drain regions of the transistors via the drain contact plugs. Each of the transistors has a first data state having a first threshold voltage and a second data state having a second threshold voltage.

Abstract: A memory includes a latch circuit latching data from a first and a second bit lines to a first and a second sense nodes; a first data line reading-out the data from the first sense node to an outside; a second data line reading-out the data from the second sense node to the outside; a first write transistor connected between the first bit line and the first or second data line without via the first and second sense node; and a second write transistor connected between the second bit line and the first or second data line without via the first and second sense node, wherein in a write operation, the first write transistor transmits the data from the first or second data line to the first bit line, or the second write transistor transmits the data from the first or second data line to the second bit line.

Abstract: A discharge lamp ballast apparatus has a reflecting mirror 2 and a power source circuit 5. The reflecting mirror 2 is disposed around a discharge light bulb 1 in such a manner as to cast light from the discharge light bulb 1 in one direction. The power source circuit 5 applies a start pulse of a negative potential with respect to the potential of the reflecting mirror 2 to an electrode 6 located at a side with the higher electric field concentration produced between electrodes 6 and 7 to which a high voltage of the start pulse is applied. This makes it possible to produce a dielectric breakdown near the electrode 6, and makes it easier to start the discharge light bulb 1.

Abstract: A memory includes memory cells, wherein during a first write operation in which first logical data is written in all memory cells connected to a first word line, a source line driver and a word line driver, the source line driver shifts a voltage of a selected source line corresponding to the first word line in a direction away from the voltage of the first word line and the word line driver shifts a voltage of a second word line in a same direction as a transition direction of voltage of a selected source line, and during a second write operation in which second logical data is written in a selected cell connected to the first word line, the source line driver and the word line driver shift voltages of the selected source line and the second word line in a direction approaching the voltage of the first word line.

Abstract: A semiconductor memory device includes: a semiconductor layer formed on an insulating layer; a plurality of transistors formed on the semiconductor layer and arranged in a matrix form, each of the transistors having a gate electrode, a source region and a drain region, the electrodes in one direction constituting word lines; source contact plugs connected to the source regions of the transistors; drain contact plugs connected to the drain regions of the transistors; source wirings each of which commonly connects the source contact plugs, the source wirings being parallel to the word lines; and bit lines formed so as to cross the word lines and connected to the drain regions of the transistors via the drain contact plugs. Each of the transistors has a first data state having a first threshold voltage and a second data state having a second threshold voltage.

Abstract: The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.

Abstract: A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.

Abstract: A high-voltage generating transformer for a discharge lamp lighting apparatus according to the present invention includes a rodlike core; a secondary winding bobbin that is divided into a plurality of sections, and where the core is disposed in the central portion thereof; a secondary winding part wound on the secondary winding bobbin, divided between the plurality of sections of the bobbin; a primary winding bobbin disposed around the outer periphery of the secondary winding part; and a primary winding part wound on the primary winding bobbin; wherein the primary winding bobbin is changed in thickness every section or every plurality of sections of the second winding part such that the bobbin has a thickened thickness on the side where the potential difference between the primary winding part and the secondary winding part is high, and the bobbin has a thinned thickness on the side where the potential difference is low.

Abstract: A semiconductor storage device according to the present invention, comprising: a first semiconductor layer formed on a substrate via a buried insulation layer; an FBC (Floating Body Cell) having a channel body of floating type formed on the first semiconductor layer, a main gate which forms a channel at a first face side of the channel body, and an auxiliary gate formed to capacitively couple on a second face at an opposite side of the first face; a logic circuit formed on the first semiconductor layer, separate from the FBC by an insulation film, which transfers a signal for the FBC; a second semiconductor layer which locates below the FBC and is formed along an under face of the buried insulation film; and a third semiconductor layer which locates below the logic circuit and is formed along an under face of the buried insulation film, wherein the second and third semiconductor layers are set to be in a potential different from each other.

Abstract: This disclosure concerns a memory comprising memory cells including floating bodies, logic data being stored in the memory cells; word lines connected to gates of the memory cells; bit lines connected to the memory cells; and sense amplifiers connected to the bit lines, and applying a first voltage to the bit lines when first logic data is written to the memory cells connected to the bit lines, wherein the sense amplifiers apply a second voltage to the memory cells having stored therein the first logic data during a refresh operation in which at least second logic data stored in the memory cells is recovered, the second logic data is opposite in logic to the first logic data, and the second voltage is lower in absolute value than the first voltage and equal to or higher in absolute value than a potential of sources of the memory cells.

Abstract: A sheet type transformer includes a primary winding 1 formed in the shape of a flat plate; and a secondary winding 6 wound around an axis perpendicular to the face of the primary winding 1, wherein the end 6a of the secondary winding 6 on the radially central side thereof is drawn out in the direction perpendicular to the face of the primary winding 1.

Abstract: A discharge lamp ballast apparatus includes a DC/DC converter having a transformer T1 and a DC/DC converter having a transformer T2, which are connected in parallel; a control section 4 for controlling the output voltages of the DC/DC converters by varying their duties with shifting the operation phases of the transformers T1 and T2 of the DC/DC converters; and a voltage-multiplier rectifier circuit having diodes 7-9 and capacitors 10-12 for generating a high voltage used for starting a discharge lamp 22 by utilizing the potential difference between the output voltages of the transformers T1 and T2.

Abstract: This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.

Abstract: An image log management device that includes a correspondence relationship information storing component, an image log data storage component, an input component and a deletion component is provided. The correspondence relationship information storing component stores correspondence relationship information between an identifier of an input document subject to image forming processing, an identifier of an output document resulting from the image forming processing of the input document, and an identifier of image log data of the output document. The image log data storage component stores the image log data of the output document. The input component inputs document disposal information including an identifier of a disposal document that has been disposed of The deletion component, based on the document disposal information and based on the correspondence relationship information, selects the image log data requiring deletion and executes deletion processing thereon.

Abstract: An optical axis control assembly is provided with a plurality of control means which are supplied with information necessary for deciding the tilt angle of the car body 1, and determine the body tilt angle by sharing the input information with the other control means; and optical axis control means for controlling the optical axis of each headlight based on the determined body tilt angle. By the combined use of a plurality of low-cost, small control devices of the same specifications each of which is incapable of determining the body tilt angle by itself because of a lack of information, the optical axis control device assembly exerts the function of determining the body tilt angle, and effects the optical axis control of the headlights based on the determined body tilt angle.

Abstract: A memory including; cells, wherein a refresh operation includes a first refresh and a second refresh, in the first refresh, a first potential higher than a gate potential in a retention is applied to the gate in a state having a source potential applied to the drain, and thereafter the gate potential in the retention is applied to the gate, thereby a first current passes to the cell, and in the second refresh, a second potential higher than a gate potential in the retention is applied to the gate, and a third potential higher than the gate potential in the retention is applied to the drain, thereby a second current passes to the cell, and a state of the cell is shifted to an equilibrium state in which amounts of the first and the second currents flowing during one cycle becomes substantially equal.

Abstract: This disclosure concerns a semiconductor memory device comprising memory cells; word lines connected to the gates of the memory cells; bit lines connected to the drains of the plurality of memory cells; sense amplifiers detecting data stored in the memory cells via the bit lines, the sense amplifiers writing data to the memory cells via the bit lines and latching read data or data to be written; and a plurality of transfer gates connecting or disconnecting the sense amplifiers to or from the bit lines, in a period of a serial access for continuously writing the data to the memory cells connected to an activated word line among the word lines, the transfer gates connecting the sense amplifiers to the bit lines corresponding to the sense amplifiers, respectively, after the sense amplifiers corresponding to the memory cells latch the data.

Abstract: A memory includes: first sense amplifiers arranged in a first interval of an arrangement of memory cell arrays, each being connected to first bit lines corresponding to two memory cell arrays provided at both sides of the first sense amplifier; second sense amplifiers arranged in a second interval of the arrangement of the memory cell arrays, each being connected to second bit lines corresponding to two memory cell arrays at both sides of the second sense amplifier; edge arrays provided beside both ends of an arrangement of the memory cell arrays, the edge arrays generating only the reference data; and edge sense amplifiers provided between the arrangement of the memory cell arrays and the edge arrays, wherein the edge sense amplifier detects data from the memory cell array at one end of the memory cell arrays based on the reference data from one of the edge arrays.