Patents by Inventor Takashi Oshikiri
Takashi Oshikiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11811759Abstract: An information processing system includes an information processing apparatus having a first function, and a server apparatus being configured to communicate with the information processing apparatus via a communication network. The information processing apparatus includes an operation control apparatus being configured to control the first function. The server apparatus transmits operation permission information indicating operation permission for the first function to the information processing apparatus, in response to satisfaction of a predetermined condition related to the information processing apparatus. The operation control apparatus activates the first function, in response to the operation permission information received by the information processing apparatus.Type: GrantFiled: July 23, 2020Date of Patent: November 7, 2023Assignee: MEGACHIPS CORPORATIONInventors: Yasuyuki Kii, Takashi Oshikiri
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Publication number: 20200358763Abstract: An information processing system includes an information processing apparatus having a first function, and a server apparatus being configured to communicate with the information processing apparatus via a communication network. The information processing apparatus includes an operation control apparatus being configured to control the first function. The server apparatus transmits operation permission information indicating operation permission for the first function to the information processing apparatus, in response to satisfaction of a predetermined condition related to the information processing apparatus. The operation control apparatus activates the first function, in response to the operation permission information received by the information processing apparatus.Type: ApplicationFiled: July 23, 2020Publication date: November 12, 2020Applicant: MegaChips CorporationInventors: Yasuyuki KII, Takashi OSHIKIRI
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Patent number: 9003202Abstract: A technique for improving data security is provided. To be specific, in a memory system including an information processing apparatus and a semiconductor memory device, the semiconductor memory device has an interface section that transmits, to the information processing apparatus, data read out from a memory core according to a plurality of communication protocols having different signal transmission/reception methods. Based on a switch command inputted from the information processing apparatus, a communication protocol selection section inputs, to the interface section, a selection signal for selecting a particular communication protocol from the plurality of communication protocols.Type: GrantFiled: April 5, 2010Date of Patent: April 7, 2015Assignee: MegaChips CorporationInventors: Takahiko Sugahara, Tetsuo Furuichi, Ikuo Yamaguchi, Takashi Oshikiri
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Patent number: 8914702Abstract: An information processing apparatus has an error correction function for checking an error of stored data read out from a flash memory. If an error is found, error information thereof is temporarily stored into a register and then stored in a nonvolatile memory at an appropriate timing. At an appropriate timing such as power-on, the information processing apparatus reads the stored data in which the error is found again on the basis of the error information stored in the nonvolatile memory, corrects the error and then rewrites the stored data into the flash memory. It is thereby possible to repair a recoverable bit error such as a read disturb. Therefore, a normal read operation can be performed without a hitch, and this can avoid giving any uncomfortable feeling to users.Type: GrantFiled: January 25, 2008Date of Patent: December 16, 2014Assignee: MegaChips CorporationInventor: Takashi Oshikiri
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Patent number: 8826042Abstract: A technique allowing an improvement in the confidentiality of information stored in a memory device. A memory controller includes a key generation part that newly generates key information for use in encryption and decryption of information at every predetermined timing, and a data conversion circuit that encrypts information to be outputted to a memory device based on the information and decrypts encrypted information inputted from the memory device based on the key information. In the data conversion circuit, each time the key generation part generates new key information, key information is updated so as to set the new key information as the key information.Type: GrantFiled: April 5, 2010Date of Patent: September 2, 2014Assignee: MegaChips CorporationInventors: Takahiko Sugahara, Tetsuo Furuichi, Ikuo Yamaguchi, Takashi Oshikiri
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Patent number: 8296500Abstract: When a memory card is inserted into a computer, a memory controller sends command information stored in a memory array to the computer. Then, the computer stores the command information received from the memory card into a RAM. The computer generates a command as needed on the basis of the stored command information and sends the generated command to the memory card. When the memory card receives the command from the computer, the memory controller analyzes the received command and performs it while making reference to command analysis information. This makes it possible to reduce a load accompanying the change and addition of commands in a semiconductor memory.Type: GrantFiled: February 12, 2008Date of Patent: October 23, 2012Assignee: MegaChips CorporationInventors: Tetsuo Furuichi, Takashi Oshikiri
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Patent number: 8261007Abstract: When a memory card is inserted into a computer, a memory controller sends command information stored in a memory array to the computer. Then, the computer stores the command information received from the memory card into a RAM. The computer generates a command as needed on the basis of the stored command information and sends the generated command to the memory card. When the memory card receives the command from the computer, the memory controller analyzes the received command and performs it while making reference to command analysis information. This makes it possible to reduce a load accompanying the change and addition of commands in a semiconductor memory.Type: GrantFiled: February 12, 2008Date of Patent: September 4, 2012Assignee: MegaChips CorporationInventors: Tetsuo Furuichi, Takashi Oshikiri
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Publication number: 20120023338Abstract: A technique for improving data security is provided. To be specific, in a memory system including an information processing apparatus and a semiconductor memory device, the semiconductor memory device has an interface section that transmits, to the information processing apparatus, data read out from a memory core according to a plurality of communication protocols having different signal transmission/reception methods. Based on a switch command inputted from the information processing apparatus, a communication protocol selection section inputs, to the interface section, a selection signal for selecting a particular communication protocol from the plurality of communication protocols.Type: ApplicationFiled: April 5, 2010Publication date: January 26, 2012Applicant: MegaChips CorporationInventors: Takahiko Sugahara, Tetsuo Furuichi, Ikuo Yamaguchi, Takashi Oshikiri
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Publication number: 20120008772Abstract: A technique allowing an improvement in the confidentiality of information stored in a memory device. A memory controller includes a key generation part that newly generates key information for use in encryption and decryption of information at every predetermined timing, and a data conversion circuit that encrypts information to be outputted to a memory device based on the information and decrypts encrypted information inputted from the memory device based on the key information. In the data conversion circuit, each time the key generation part generates new key information, key information is updated so as to set the new key information as the key information.Type: ApplicationFiled: April 5, 2010Publication date: January 12, 2012Applicant: MEGACHIPS CORPORATIONInventors: Takahiko Sugahara, Tetsuo Furuichi, Ikuo Yamaguchi, Takashi Oshikiri
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Patent number: 8090958Abstract: A memory-specific tester has a buffer storing input pattern data and output expectation data. An address included in the input pattern data read from the buffer is sent to a semiconductor memory, and is then subjected to descrambling at a security circuit. The descrambled address is converted at an address conversion circuit to an address designating a region for storing a check pattern in a memory core. Data given from the memory core (check pattern) is subjected to scrambling at the security circuit, and is then sent to the memory-specific tester. The memory-specific tester makes comparison between expectation data and the data read from the semiconductor memory.Type: GrantFiled: October 31, 2005Date of Patent: January 3, 2012Inventor: Takashi Oshikiri
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Patent number: 8015416Abstract: An information processing apparatus causes an encryption key data generating section to generate key data stored in a semiconductor memory by using encryption key source data read from the semiconductor memory and cipher generation data stored therein, and stores the key data in a temporary storage section. The information processing apparatus transmits data encrypted by an encryption circuit by using the key data. Upon receipt of the encrypted data, the semiconductor memory executes a command decrypted by a decryption circuit similarly using the key data. This achieves data communication only between the predetermined semiconductor memory and the information processing apparatus.Type: GrantFiled: August 16, 2005Date of Patent: September 6, 2011Assignees: Megachips Corporation, Nintendo Co., Ltd.Inventors: Takanobu Nakashima, Takashi Oshikiri
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Patent number: 7941589Abstract: A semiconductor memory (2) comprises a controller (21) and a memory array (22). The memory array (22) is controlled for each of block areas (221, 221 . . . ). The information processing apparatus (1) can not generate a data erase command for each block area (221). A data erase command (30) for a specified block area “G” is encoded and stored in a block area “A”. When a request for data erasing is issued, a CPU (11) of the information processing apparatus (1) reads an erase command (30) out from the semiconductor memory (2) and outputs the erase command (30) to the controller (21). The controller (21) decodes the erase command (30) and performs a data erasing process for the block area “G”.Type: GrantFiled: October 29, 2007Date of Patent: May 10, 2011Assignee: MegaChips CorporationInventor: Takashi Oshikiri
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Patent number: 7861057Abstract: A memory is provided which simplifies the manufacturing process on the supplier side while satisfying specifications provided from the user side. An address space of a memory core includes an information storage region, a code region, and a no-write region. The information storage region includes a first region where no-write region information is written and a second region where a fixed value is written. Program code is written in the code region. The no-write region information indicates the position of the no-write region, and the fixed value indicates a fixed value that is intended to be written to the no-write region. The ROM selects between the fixed value and original read data that is obtained by a data selecting section directly from the memory core, and outputs the selected one as read data.Type: GrantFiled: September 10, 2007Date of Patent: December 28, 2010Assignee: MegaChips CorporationInventor: Takashi Oshikiri
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Patent number: 7739467Abstract: While a semiconductor memory operates in a first operation mode with high security, an encrypted command is inputted and then decoded to acquire the first address information. After the semiconductor memory comes into a second operation mode where the level of security is lower than that of the first operation mode, a command is inputted. Then, the second address information is acquired from the command. A control circuit in the semiconductor memory generates an address of 10 bits by using the first address information as a high-order 4 bits and the second address information as a low-order 6 bits and outputs the address to a memory array. With this operation, it becomes possible to read/write data from/to the memory array.Type: GrantFiled: January 30, 2007Date of Patent: June 15, 2010Assignee: MegaChips CorporationInventor: Takashi Oshikiri
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Patent number: 7663920Abstract: An object of the present invention is to provide a memory system that offers enhanced security of ROM code that is data whose contents can be utilized for a given purpose in its intact form. In a memory system, data is read from a memory according to at least two or more addresses outputted from an address generator, from individual pages uniquely specified respectively by the addresses. A data generator generates one piece of data on the basis of the at least two or more pieces of data read from the individual pages.Type: GrantFiled: August 2, 2007Date of Patent: February 16, 2010Assignee: MegaChips CorporationInventor: Takashi Oshikiri
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Patent number: 7565476Abstract: The present invention provides a memory device of a type that outputs a ready signal to the outside, and that is capable of achieving an enhanced data transfer rate and a uniform latency time. A memory device according to the present invention includes a ready signal sending portion, and the ready signal sending portion monitors a memory portion to detect the memory portion becoming ready for reading or writing of specified data. The ready signal sending portion generates a first ready signal that changes from a busy state to a ready state after the detection and an enabling signal that changes from a disable state to an enable state on the basis of a preset ready generating timing value. When the first ready signal is in the ready state and the enabling signal is in the enable state, the ready signal sending portion sends to the outside a second ready signal that is in a ready state.Type: GrantFiled: November 2, 2006Date of Patent: July 21, 2009Assignee: MegaChips LSI Solutions Inc.Inventor: Takashi Oshikiri
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Patent number: 7492650Abstract: The present invention provides a semiconductor storage device that requires no specialized circuit or the like for reading redundancy data from a redundancy region, and that is capable of freely changing the arrangement of the redundancy region in the memory array area. A semiconductor storage device of the present invention includes a memory array configured as shown below. The memory array includes a user region which is composed of given page units and where user data is stored, and a redundancy region which is composed of the same given page units and where redundancy data is stored. The area in the memory array can be used either as the user region or as the redundancy region.Type: GrantFiled: December 20, 2006Date of Patent: February 17, 2009Assignee: MegaChips LSI Solutions Inc.Inventors: Kumiko Mito, Takashi Oshikiri
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Publication number: 20080244175Abstract: When a memory card is inserted into a computer, a memory controller sends command information stored in a memory array to the computer. Then, the computer stores the command information received from the memory card into a RAM. The computer generates a command as needed on the basis of the stored command information and sends the generated command to the memory card. When the memory card receives the command from the computer, the memory controller analyzes the received command and performs it while making reference to command analysis information. This makes it possible to reduce a load accompanying the change and addition of commands in a semiconductor memory.Type: ApplicationFiled: February 12, 2008Publication date: October 2, 2008Applicant: MegaChips CorporationInventors: Tetsuo Furuichi, Takashi Oshikiri
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Publication number: 20080229002Abstract: A semiconductor memory (2) comprises a controller (21) and a memory array (22). The memory array (22) is controlled for each of block areas (221, 221 . . . ). The information processing apparatus (1) can not generate a data erase command for each block area (221). A data erase command (30) for a specified block area “G” is encoded and stored in a block area “A”. When a request for data erasing is issued, a CPU (11) of the information processing apparatus (1) reads an erase command (30) out from the semiconductor memory (2) and outputs the erase command (30) to the controller (21). The controller (21) decodes the erase command (30) and performs a data erasing process for the block area “G”.Type: ApplicationFiled: October 29, 2007Publication date: September 18, 2008Applicant: MegaChips CorporationInventor: Takashi OSHIKIRI
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Publication number: 20080215954Abstract: An information processing apparatus has an error correction function for checking an error of stored data read out from a flash memory. If an error is found, error information thereof is temporarily stored into a register and then stored in a nonvolatile memory at an appropriate timing. At an appropriate timing such as power-on, the information processing apparatus reads the stored data in which the error is found again on the basis of the error information stored in the nonvolatile memory, corrects the error and then rewrites the stored data into the flash memory. It is thereby possible to repair a recoverable bit error such as a read disturb. Therefore, a normal read operation can be performed without a hitch, and this can avoid giving any uncomfortable feeling to users.Type: ApplicationFiled: January 25, 2008Publication date: September 4, 2008Applicant: MegaChips CorporationInventor: Takashi OSHIKIRI