Abstract: In a semiconductor device which calculates an interaction model, a technique capable of executing interaction calculation in non-synchronization with a clock is provided. The semiconductor device includes a plurality of units each of which includes: a first memory cell for storing a value indicating a state of one node of an interaction model; a second memory cell for storing an interaction coefficient indicating an interaction from a node connected to the one node; and an interaction calculation circuit for determining a value indicating a next state of the one node based on a current determined by a value indicating a state of the connected node and the interaction coefficient.

Abstract: The present invention provides a semiconductor device and a failure detection method capable of detecting an excessive variation among elements that constitute an analog circuit as a failure. According to an embodiment, a semiconductor device 1 includes: an AD converter 11; a digital assist circuit 12 that corrects an error of a digital signal Do corresponding to an analog signal Ain processed by the AD converter 11; and a failure detection circuit 13 that detects whether the AD converter 11 has a failure based on a correction amount by the digital assist circuit. The semiconductor device 1 is therefore able to detect the excessive variation among the elements that constitute the AD converter 11 as a failure.

Abstract: Provided is an analog-to-digital converter capable of suppressing an increase in an occupation area. The analog-to-digital converter includes a multiplying digital-to-analog conversion circuit which includes a capacitance circuit that samples and amplifies an input signal, a quantizer that quantizes the input signal, and a control circuit that determines a voltage to be supplied to the capacitance circuit in accordance with an output from the quantizer. The capacitance circuit includes a first capacitance element and a second capacitance element, each of which includes a first electrode to which a normal phase signal corresponding to the input signal is supplied and a second electrode to which an opposite phase signal is supplied when the input signal is sampled. When the input signal is amplified, an output from the control circuit is supplied to the respective second electrodes, and signals from the respective first electrodes are regarded as amplified residual error amplified signal.

Abstract: Improvement of conversion precision in an analog-to-digital converter is realized. Therefore, a voltage of a correction signal and a voltage obtained by attenuating the voltage with a fixed attenuation rate by an attenuation circuit 21 are generated and each voltage is input to an analog-to-digital conversion unit 23. A correction unit 20a receives a digital output from the analog-to-digital conversion unit 23, searches a correction coefficient Wi of each bit of the analog-to-digital conversion unit 23, based on an adaptive control algorithm, and corrects the digital output from the analog-to-digital conversion unit 23 using the searched correction coefficient Wi.

Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.

Abstract: There is provided a semiconductor device using low electric power and a small area which can realize highly accurate calibration. The semiconductor device according to the embodiment includes an A/D conversion unit, and a hold signal generating circuit which is coupled to an input side of the A/D conversion unit, and has a hold period not less than two cycles of the A/D conversion unit. The hold signal generating circuit includes: an SC integrator including an input buffer coupled to the input side of the A/D conversion unit, and feedback capacitor coupled to an input and an output of the input buffer; and a logic circuit which compares an output signal of plural bits outputted from the A/D conversion unit with a first and a second threshold values, and outputs a control signal which controls polarity of the SC integrator according to a comparison result.

Abstract: Improvement of conversion precision in an analog-to-digital converter is realized. Therefore, a voltage of a correction signal and a voltage obtained by attenuating the voltage with a fixed attenuation rate by an attenuation circuit 21 are generated and each voltage is input to an analog-to-digital conversion unit 23. A correction unit 20a receives a digital output from the analog-to-digital conversion unit 23, searches a correction coefficient Wi of each bit of the analog-to-digital conversion unit 23, based on an adaptive control algorithm, and corrects the digital output from the analog-to-digital conversion unit 23 using the searched correction coefficient Wi.

Abstract: It is a problem that each ADC sampling circuit connected in parallel in an interleaved ADC releases an electric charge depending on an input signal when sampling is performed and other ADCs connected in parallel sample the input signal disturbed thereby so that resolution of the interleaved ADC is decreased. The problem is improved by inputting a common differential sampling clock signal to one set of two ADCs which is sampled at a ?-phase shift of each ADC connected in parallel in a time interleaved ADC, providing an individual buffer in a prior stage of an input sampling circuit, isolating a common analog input signal line from an ADC input terminal, and digitally correcting characteristics degradation by insertion of the buffer.

Abstract: Provided is an analog-to-digital converter capable of suppressing an increase in an occupation area. The analog-to-digital converter includes a multiplying digital-to-analog conversion circuit which includes a capacitance circuit that samples and amplifies an input signal, a quantizer that quantizes the input signal, and a control circuit that determines a voltage to be supplied to the capacitance circuit in accordance with an output from the quantizer. The capacitance circuit includes a first capacitance element and a second capacitance element, each of which includes a first electrode to which a normal phase signal corresponding to the input signal is supplied and a second electrode to which an opposite phase signal is supplied when the input signal is sampled. When the input signal is amplified, an output from the control circuit is supplied to the respective second electrodes, and signals from the respective first electrodes are regarded as amplified residual error amplified signal.

Abstract: An acceleration sensor that achieves a simultaneous operation method of a signal detection and a servo control is provided as an alternative to a time-division processing method. The acceleration sensor is a MEMS capacitive acceleration sensor. The acceleration sensor includes signal detection capacitor pairs 12, 15, and DC servo control capacitor pairs 13, 16, and AC servo control capacitor pairs 14, 17, which are different from the signal detection capacitor pairs 12, 15. A voltage that generates a force in a direction opposite to a detection signal of acceleration detected by the signal detection capacitor pairs 12, 15 is applied to the DC servo control capacitor pairs 13, 16 and the AC servo control capacitor pairs 14, 17.

Abstract: A low-noise and high-sensitivity inertial sensor is provided. On the assumption that a movable portion VU1 and a movable portion VU2 are formed in the same SOI layer, the movable portion VU1 and the movable portion VU2 are mechanically connected to each other by a mechanical coupling portion MCU even while these movable portions are electrically isolated from each other. Thereby, according to a sensor element SE in the invention, it is possible to further suppress a shift between the capacitance of a MEMS capacitor 1 and the capacitance of a MEMS capacitor 2.

Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.

Abstract: In a semiconductor device which calculates an interaction model, a technique capable of executing interaction calculation in non-synchronization with a clock is provided. The semiconductor device includes a plurality of units each of which includes: a first memory cell for storing a value indicating a state of one node of an interaction model; a second memory cell for storing an interaction coefficient indicating an interaction from a node connected to the one node; and an interaction calculation circuit for determining a value indicating a next state of the one node based on a current determined by a value indicating a state of the connected node and the interaction coefficient.

Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.

Abstract: To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.

Abstract: In a system including analog circuits of multichannel, channels which have a short distance therebetween are grouped so as to be included in the same group. During a reception period, a common correction signal is supplied to master channels allocated to the respective groups, and received signals are supplied to slave channels other than the master channels. A correction coefficient which tracks a characteristic fluctuation of each group is continuously searched for through continuous comparison between outputs of the respective master channels, and an output of each slave channel is corrected by using the correction coefficient of a group including the slave channel.

Abstract: There is provided a semiconductor device using low electric power and a small area which can realize highly accurate calibration. The semiconductor device according to the embodiment includes an A/D conversion unit, and a hold signal generating circuit which is coupled to an input side of the A/D conversion unit, and has a hold period not less than two cycles of the A/D conversion unit. The hold signal generating circuit includes: an SC integrator including an input buffer coupled to the input side of the A/D conversion unit, and feedback capacitor coupled to an input and an output of the input buffer; and a logic circuit which compares an output signal of plural bits outputted from the A/D conversion unit with a first and a second threshold values, and outputs a control signal which controls polarity of the SC integrator according to a comparison result.

Abstract: It is a problem that each ADC sampling circuit connected in parallel in an interleaved ADC releases an electric charge depending on an input signal when sampling is performed and other ADCs connected in parallel sample the input signal disturbed thereby so that resolution of the interleaved ADC is decreased. The problem is improved by inputting a common differential sampling clock signal to one set of two ADCs which is sampled at a ?-phase shift of each ADC connected in parallel in a time interleaved ADC, providing an individual buffer in a prior stage of an input sampling circuit, isolating a common analog input signal line from an ADC input terminal, and digitally correcting characteristics degradation by insertion of the buffer.

Abstract: According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory, a temporary storage buffer that temporarily stores writing data to be written to the nonvolatile semiconductor memory, and a coding processing unit that divides coding target data of an error correction code into two or more divided data and writes an error correction code obtained by performing an error correction coding process based on the divided data stored in the temporary storage buffer to the temporary storage buffer as an intermediate code.

Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.