Patents by Inventor Takashi Oshima
Takashi Oshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150249459Abstract: To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.Type: ApplicationFiled: May 13, 2015Publication date: September 3, 2015Inventors: Takashi OSHIMA, Tatsuji MATSUURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO, Keisuke KIMURA
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Publication number: 20150236737Abstract: In a system including analog circuits of multichannel, channels which have a short distance therebetween are grouped so as to be included in the same group. During a reception period, a common correction signal is supplied to master channels allocated to the respective groups, and received signals are supplied to slave channels other than the master channels. A correction coefficient which tracks a characteristic fluctuation of each group is continuously searched for through continuous comparison between outputs of the respective master channels, and an output of each slave channel is corrected by using the correction coefficient of a group including the slave channel.Type: ApplicationFiled: January 12, 2015Publication date: August 20, 2015Inventors: Yuki Okada, Takashi Oshima
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Publication number: 20150229322Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.Type: ApplicationFiled: April 21, 2015Publication date: August 13, 2015Inventors: Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO, Keisuke KIMURA, Takashi OSHIMA, Tatsuji MATSUURA
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Patent number: 9100034Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.Type: GrantFiled: March 10, 2014Date of Patent: August 4, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Oshima, Tatsuji Matsuura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto, Keisuke Kimura
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Patent number: 9054726Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.Type: GrantFiled: January 21, 2014Date of Patent: June 9, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichi Okuda, Hideo Nakane, Takaya Yamamoto, Keisuke Kimura, Takashi Oshima, Tatsuji Matsuura
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Patent number: 9054723Abstract: To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.Type: GrantFiled: May 12, 2014Date of Patent: June 9, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Oshima, Tatsuji Matsuura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto, Keisuke Kimura
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Patent number: 8933831Abstract: The influence of a jitter of a sampling clock of an analog-to-digital converter is digitally corrected at low power consumption. The sampling clock of the analog-to-digital converter is generated by a phase locked loop (PLL) using a reference clock, which has a lower frequency and lower jitter than the sampling clock, as a source oscillation. A time-to-digital converter (TDC) converts a timing error at a timing where the sampling clock and the reference clock are synchronized with each other into a digital value. A timing error at a sampling timing where the reference clock is not present is generated by interpolating a detected timing error. Thus, a jitter value of the sampling clock at each sampling timing is obtained. A sampling voltage error is calculated from the jitter value and the output of the analog-to-digital converter is digitally corrected.Type: GrantFiled: August 8, 2012Date of Patent: January 13, 2015Assignee: Hitachi, Ltd.Inventors: Takashi Oshima, Yohei Nakamura
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Patent number: 8922407Abstract: A reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. Samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.Type: GrantFiled: April 30, 2014Date of Patent: December 30, 2014Assignee: Hitachi, Ltd.Inventors: Takashi Oshima, Taizo Yamawaki, Tomomi Takahashi
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Publication number: 20140333459Abstract: To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.Type: ApplicationFiled: May 12, 2014Publication date: November 13, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takashi OSHIMA, Tatsuji MATSUURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO, Keisuke KIMURA
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Publication number: 20140253352Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.Type: ApplicationFiled: March 10, 2014Publication date: September 11, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takashi OSHIMA, Tatsuji MATSUURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO, Keisuke KIMURA
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Publication number: 20140232578Abstract: A reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. Samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.Type: ApplicationFiled: April 30, 2014Publication date: August 21, 2014Applicant: HITACHI, LTD.Inventors: Takashi OSHIMA, Taizo YAMAWAKI, Tomomi TAKAHASHI
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Publication number: 20140203958Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.Type: ApplicationFiled: January 21, 2014Publication date: July 24, 2014Applicant: Renesas Electronics CorporationInventors: Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO, Keisuke KIMURA, Takashi OSHIMA, Tatsuji MATSUURA
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Patent number: 8736470Abstract: A reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. Samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.Type: GrantFiled: December 28, 2011Date of Patent: May 27, 2014Assignee: Hitachi, Ltd.Inventors: Takashi Oshima, Taizo Yamawaki, Tomomi Takahashi
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Patent number: 8525712Abstract: To improve resolution of a built-in A/D converter by reducing the area occupied by a chip of the built-in A/D converter in a semiconductor integrated circuit that is mounted in an on-vehicle millimeter wave radar device and which incorporates an A/D converter and an MPU. In the semiconductor integrated circuit, a plurality of reception signals of the radar device is A/D-converted by a single digital correction type A/D converter. The digital correction type A/D converter of the single A/D converter is a foreground digital correction type A/D converter that sequentially A/D-converts the reception signals output from a multiplexer of a receiving interface. The single A/D converter includes a pipeline type A/D converter having a plurality of cascade-coupled converters. The semiconductor integrated circuit comprises a correction signal generating unit, a digital correction D/A converter, and a digital correction unit for digital correction.Type: GrantFiled: August 1, 2011Date of Patent: September 3, 2013Assignee: Renesas Electronics CorporationInventors: Takashi Oshima, Tatsuji Matsuura, Naoki Yada, Takahiro Miki, Akihiro Kitagawa, Tetsuo Matsui, Kunihiko Usui
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Publication number: 20130191705Abstract: According to an embodiment, a semiconductor storage device includes an error correction processing unit that executes encoding process related data to be dispersedly written over a plurality of memory areas and decoding process related data dispersedly written over the plurality of memory areas. A transfer management unit determines whether or not data related to the data transfer request is a target of the error correction process and causes the error correction processing unit to execute the error correction process only with respect to the data determined as the target of the error correction process.Type: ApplicationFiled: December 15, 2011Publication date: July 25, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Kouji Watanabe, Toshikatsu Hida, Takashi Oshima
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Publication number: 20130179750Abstract: According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory, a temporary storage buffer that temporarily stores writing data to be written to the nonvolatile semiconductor memory, and a coding processing unit that divides coding target data of an error correction code into two or more divided data and writes an error correction code obtained by performing an error correction coding process based on the divided data stored in the temporary storage buffer to the temporary storage buffer as an intermediate code.Type: ApplicationFiled: December 15, 2011Publication date: July 11, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Toshikatsu Hida, Takashi Oshima, Kouji Watanabe
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Patent number: 8456335Abstract: In a successive approximation ADC, resolution is limited because a distortion occurs in an A/D conversion result due to a voltage dependence of a sampling capacitance. An A/D converter includes a sampling capacitor part in which capacitors equal in capacitance value to each other are connected inversely, a successive approximation A/D conversion part that conducts A/D conversion on the sampling charge, a digital correction part that corrects capacitance variation of internal DAC capacitors in the successive approximation A/D conversion part, and a digital correction part that digitally corrects a third-order or more factor of a voltage dependence of the sampling charge.Type: GrantFiled: November 16, 2011Date of Patent: June 4, 2013Assignee: Hitachi, Ltd.Inventor: Takashi Oshima
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Publication number: 20130058437Abstract: The influence of a jitter of a sampling clock of an analog-to-digital converter is digitally corrected at low power consumption. The sampling clock of the analog-to-digital converter is generated by a phase locked loop (PLL) using a reference clock, which has a lower frequency and lower jitter than the sampling clock, as a source oscillation. A time-to-digital converter (TDC) converts a timing error at a timing where the sampling clock and the reference clock are synchronized with each other into a digital value. Incidentally, a timing error at a sampling timing where the reference clock is not present is generated by interpolating a detected timing error. Thus, a jitter value of the sampling clock at each sampling timing is obtained. A sampling voltage error is calculated from the jitter value and the output of the analog-to-digital converter is digitally corrected.Type: ApplicationFiled: August 8, 2012Publication date: March 7, 2013Inventors: Takashi OSHIMA, Yohei Nakamura
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Publication number: 20130049999Abstract: A reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. Samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.Type: ApplicationFiled: December 28, 2011Publication date: February 28, 2013Inventors: TAKASHI OSHIMA, Taizo Yamawaki, Tomomi Takahashi
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Publication number: 20120133534Abstract: In a successive approximation ADC, resolution is limited because a distortion occurs in an A/D conversion result due to a voltage dependence of a sampling capacitance. An A/D converter includes a sampling capacitor part in which capacitors equal in capacitance value to each other are connected inversely, a successive approximation A/D conversion part that conducts A/D conversion on the sampling charge, a digital correction part that corrects capacitance variation of internal DAC capacitors in the successive approximation A/D conversion part, and a digital correction part that digitally corrects a third-order or more factor of a voltage dependence of the sampling charge.Type: ApplicationFiled: November 16, 2011Publication date: May 31, 2012Applicant: Hitachi, Ltd.Inventor: Takashi OSHIMA