Patents by Inventor Takashi Shigematsu

Takashi Shigematsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10122095
    Abstract: A crimp terminal includes a crimp portion formed in a tubular shape with an electrically conductive the substrate and configured to crimp join with an electric wire, and a sealing portion formed at one end of the crimp portion and seals against an electric wire to be crimp joined to the crimp portion. At the sealing portion, the substrate is bent and lapped and continuously joined from one end portion to another end portion of this overlapped portion. One end of a joining trajectory is at a position that is deviated on a side opposite of the crimp portion with respect to the sealing portion.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: November 6, 2018
    Assignees: FURUKAWA ELECTRIC CO., LTD., FURUKAWA AUTOMOTIVE SYSTEMS INC.
    Inventors: Shinya Kojima, Saburo Yagi, Takashi Shigematsu
  • Patent number: 9985405
    Abstract: A terminal manufacturing apparatus includes a pressing device adapted to form a chained terminal including a crimp portion by bending a continuously supplied plate-shaped workpiece into a hollow shape, the crimp portion being crimpable with a conductor part of a coated conductor accommodated therein, a welding device adapted to bring two edge portions of the crimp portion in proximity to each other and join the two edge portions by welding, a conveying/positioning time calculating unit adapted to determine a conveying/positioning time of the welding device on the basis of a machining time required by the pressing device and the welding device, and a conveying/positioning mechanism adapted to position the chained terminal in a welding machining position within the welding device in accordance with the conveying/positioning time.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: May 29, 2018
    Assignees: FURUKAWA AUTOMOTIVE SYSTEMS INC., FURUKAWA ELECTRIC CO., LTD.
    Inventors: Shinya Kojima, Masaya Satou, Takashi Shigematsu, Saburo Yagi, Kentarou Sakamoto, Mikio Kuwahara
  • Publication number: 20170301974
    Abstract: The present invention is aimed at providing a waveguide coupling that enables two waveguides to be easily connected together while aligning cross sections of the two waveguides to hold central axes of the two waveguides concentrically with high accuracy. A coupling is for use in connecting two waveguides in an axial direction. The coupling includes a continuous body and a ring member. The continuous body is used to surround in a circumferential direction a connecting portion connecting the two waveguides. The continuous body includes seven partitioning bodies hinged at six portions by gudgeons to become continuous, and the partitioning bodies of end portions are connected together with screws, whereby the continuous body is formed annularly. The ring member has an annular shape, is disposed along a circumference of the waveguide, and is connected to the continuous body by screws.
    Type: Application
    Filed: May 24, 2013
    Publication date: October 19, 2017
    Inventors: Tetsuji SAITO, Yasumasa TANAKA, Masatsugu SAKAGUCHI, Takashi SHIGEMATSU
  • Patent number: 9694443
    Abstract: A laser welding apparatus that welds a butted interface of a workpiece by laser light irradiation while successively feeding the workpiece having the butted interface to a welding position includes an X- and Y-axis scanner that scans laser light outputted from a laser light source in an X-axis direction and a Y-axis direction which are orthogonal to each other, a measuring device that measures a dimension along the butted interface, and a scanner control device that controls driving of the X- and Y-axis scanner so as to weld the butted interface by laser light irradiation.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: July 4, 2017
    Assignee: Furukawa Automotive Systems Inc.
    Inventors: Saburo Yagi, Takashi Shigematsu, Masaya Satou, Shinya Kojima
  • Publication number: 20170162953
    Abstract: A crimp terminal includes a crimp portion formed in a tubular shape with an electrically conductive the substrate and configured to crimp join with an electric wire, and a sealing portion formed at one end of the crimp portion and seals against an electric wire to be crimp joined to the crimp portion. At the sealing portion, the substrate is bent and lapped and continuously joined from one end portion to another end portion of this overlapped portion. One end of a joining trajectory is at a position that is deviated on a side opposite of the crimp portion with respect to the sealing portion.
    Type: Application
    Filed: February 15, 2017
    Publication date: June 8, 2017
    Applicants: FURUKAWA ELECTRIC CO., LTD., FURUKAWA AUTOMOTIVE SYSTEMS INC.
    Inventors: Shinya KOJIMA, Saburo YAGI, Takashi SHIGEMATSU
  • Patent number: 9564691
    Abstract: A method for manufacturing a crimp terminal having a crimp portion that allows crimp connection to a conductor part of a coated wire includes forming a tubular body by bringing together side edges of a plate material made of metal composed of a copper alloy having a copper content ratio of greater than or equal to 70%, irradiating a periphery of the sides edges, which are brought together, with laser light from a laser irradiation unit to weld the side edges which are brought together, and setting a power density of the laser light and a sweep rate of the laser light in such a manner that a weld bead formed at the side edge portion after the welding has a width of 80 ?m to 390 ?m.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: February 7, 2017
    Assignees: FURUKAWA AUTOMOTIVE SYSTEMS INC., FURUKAWA ELECTRIC CO., LTD.
    Inventors: Saburo Yagi, Takashi Shigematsu, Masaya Satou, Shinya Kojima, Akira Tachibana
  • Patent number: 9391376
    Abstract: In a female crimp terminal including a pressure-bonding section for permitting pressure-bonding and connection to an aluminum core wire of an insulated wire, the pressure-bonding section is configured in a hollow sectional shape by a plate material, and a long length direction weld portion in a long length direction is welded, a forward part in the hollow sectional shape is caused to take an almost flat plate-shaped sealing shape and a width direction weld portion in a width direction is welded.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: July 12, 2016
    Assignees: Furukawa Electric Co., Ltd., Furukawa Automotive Systems, Inc.
    Inventors: Yukihiro Kawamura, Satoshi Takamura, Takashi Tonoike, Yasushi Kihara, Saburo Yagi, Takashi Shigematsu, Kengo Mitose, Takashi Kayahara
  • Patent number: 9275863
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: March 1, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20150364837
    Abstract: A method for manufacturing a crimp terminal having a crimp portion that allows crimp connection to a conductor part of a coated wire includes forming a tubular body by bringing together side edges of a plate material made of metal composed of a copper alloy having a copper content ratio of greater than or equal to 70%, irradiating a periphery of the sides edges, which are brought together, with laser light from a laser irradiation unit to weld the side edges which are brought together, and setting a power density of the laser light and a sweep rate of the laser light in such a manner that a weld bead formed at the side edge portion after the welding has a width of 80 ?m to 390 ?m.
    Type: Application
    Filed: August 21, 2015
    Publication date: December 17, 2015
    Inventors: Saburo YAGI, Takashi SHIGEMATSU, Masaya SATOU, Shinya KOJIMA, Akira TACHIBANA
  • Publication number: 20150364891
    Abstract: A terminal manufacturing apparatus includes a pressing device adapted to form a chained terminal including a crimp portion by bending a continuously supplied plate-shaped workpiece into a hollow shape, the crimp portion being crimpable with a conductor part of a coated conductor accommodated therein, a welding device adapted to bring two edge portions of the crimp portion in proximity to each other and join the two edge portions by welding, a conveying/positioning time calculating unit adapted to determine a conveying/positioning time of the welding device on the basis of a machining time required by the pressing device and the welding device, and a conveying/positioning mechanism adapted to position the chained terminal in a welding machining position within the welding device in accordance with the conveying/positioning time.
    Type: Application
    Filed: August 21, 2015
    Publication date: December 17, 2015
    Inventors: Shinya KOJIMA, Masaya SATOU, Takashi SHIGEMATSU, Saburo YAGI, Kentarou SAKAMOTO, Mikio KUWAHARA
  • Publication number: 20150360319
    Abstract: A laser welding apparatus that welds a butted interface of a workpiece by laser light irradiation while successively feeding the workpiece having the butted interface to a welding position includes an X- and Y-axis scanner that scans laser light outputted from a laser light source in an X-axis direction and a Y-axis direction which are orthogonal to each other, a measuring device that measures a dimension along the butted interface, and a scanner control device that controls driving of the X- and Y-axis scanner so as to weld the butted interface by laser light irradiation.
    Type: Application
    Filed: August 21, 2015
    Publication date: December 17, 2015
    Inventors: Saburo YAGI, Takashi SHIGEMATSU, Masaya SATOU, Shinya KOJIMA
  • Publication number: 20150126078
    Abstract: In a female crimp terminal including a pressure-bonding section for permitting pressure-bonding and connection to an aluminum core wire of an insulated wire, the pressure-bonding section is configured in a hollow sectional shape by a plate material, and a long length direction weld portion in a long length direction is welded, a forward part in the hollow sectional shape is caused to take an almost flat plate-shaped sealing shape and a width direction weld portion in a width direction is welded.
    Type: Application
    Filed: January 5, 2015
    Publication date: May 7, 2015
    Applicants: Furukawa Electric Co., Ltd., Furukawa Automotive Systems, Inc.
    Inventors: Yukihiro KAWAMURA, Satoshi TAKAMURA, Takashi TONOIKE, Yasushi KIHARA, Saburo YAGI, Takashi SHIGEMATSU, Kengo MITOSE, Takashi KAYAHARA
  • Publication number: 20150011081
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: September 22, 2014
    Publication date: January 8, 2015
    Inventors: Sumito NUMAZAWA, Yoshito NAKAZAWA, Masayoshi KOBAYASHI, Satoshi KUDO, Yasuo IMAI, Sakae KUBO, Takashi SHIGEMATSU, Akihiro OHNISHI, Kozo UESAWA, Kentaro OISHI
  • Publication number: 20140225189
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: April 23, 2014
    Publication date: August 14, 2014
    Applicants: RENESAS ELECTRONICS CORPORATION, HITACHI ULSI SYSTEMS CO., LTD.
    Inventors: Sumito NUMAZAWA, Yoshito NAKAZAWA, Masayoshi KOBAYASHI, Satoshi KUDO, Yasuo IMAI, Sakae KUBO, Takashi SHIGEMATSU, Akihiro OHNISHI, Kozo UESAWA, Kentaro OISHI
  • Publication number: 20140216340
    Abstract: Disclosed is a method of producing an insulated electric wire, in which a primary coating layer including at least an enamel-baking layer is formed on a metallic conductor to form a primary coated electric wire, and a secondary coating layer is extrusion-formed on the primary coating layer of the primary coated electric wire. The method includes an electric wire pre-heating process where a surface of the primary coating layer is pre-heated using an electric wire pre-heating unit, and a resin extrusion process where a secondary coating layer is extrusion-formed on the pre-heated primary coating layer using a resin extrusion unit. Further disclosed is an apparatus for producing an insulated electric wire.
    Type: Application
    Filed: April 10, 2014
    Publication date: August 7, 2014
    Applicant: Furukawa Electric Co., Ltd.
    Inventors: Hiroyuki KUSAKA, Koji KUROMIYA, Satoshi SAITO, Takashi SHIGEMATSU, Akihiro MURAKAMI, Shinji ICHIKAWA, Haruo SAKUMA, Shingo NISHIJIMA
  • Patent number: 8790747
    Abstract: Disclosed is a method of producing an insulated electric wire, in which a primary coating layer including at least an enamel-baking layer is formed on a metallic conductor to form a primary coated electric wire, and a secondary coating layer is extrusion-formed on the primary coating layer of the primary coated electric wire. The method includes an electric wire pre-heating process where a surface of the primary coating layer is pre-heated using an electric wire pre-heating unit, and a resin extrusion process where a secondary coating layer is extrusion-formed on the pre-heated primary coating layer using a resin extrusion unit. Further disclosed is an apparatus for producing an insulated electric wire.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: July 29, 2014
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Hiroyuki Kusaka, Koji Kuromiya, Satoshi Saito, Takashi Shigematsu, Akihiro Murakami, Shinji Ichikawa, Haruo Sakuma, Shingo Nishijima
  • Patent number: 8748266
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: June 10, 2014
    Assignees: Renesas Electronics Corporation, Hitachi Ulsi Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 8354713
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: January 15, 2013
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20120052675
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: November 8, 2011
    Publication date: March 1, 2012
    Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 8076202
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: December 13, 2011
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi