Patents by Inventor Takashi Tonegawa
Takashi Tonegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230411323Abstract: A dielectric layer has a first opening exposing a surface of a first conductive layer and a second opening exposing a surface of a second conductive layer and having an opening area smaller than an opening area of the first opening. A material of the surface of the second conductive layer exposed from the second opening is different from a material of the surface of the first conductive layer exposed from the first opening, and includes aluminum.Type: ApplicationFiled: March 23, 2023Publication date: December 21, 2023Inventors: Etsuko WATANABE, Takashi TONEGAWA
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Patent number: 11652072Abstract: To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.Type: GrantFiled: April 8, 2021Date of Patent: May 16, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Tonegawa, Hiroshi Inagawa
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Publication number: 20230111921Abstract: First conductive layer is connected to an impurity region which is a source region or an emitter region. A first conductive layer having an emitter pad and a second conductive layer having a Kelvin emitter pad and a relay pad are separated. A plane occupied area of the Kelvin emitter pad is smaller than a plane occupied area of the emitter pad.Type: ApplicationFiled: August 11, 2022Publication date: April 13, 2023Inventor: Takashi TONEGAWA
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Patent number: 11456265Abstract: A method of manufacturing a semiconductor device includes forming an interlayer insulating film over a main surface of a semiconductor substrate, forming a first conductive film pattern for a first pad and a second conductive film pattern for a second pad over the interlayer insulating film, forming an insulating film over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns, forming a first opening portion for the first pad, the first opening portion exposing a portion of the first conductive film pattern, and a second opening portion for the second pad, the second opening portion exposing a portion of the second conductive film pattern, in the insulating film, and forming a first plated layer by plating over the portion of the first conductive film pattern exposed in the first opening portion, and a second plated layer.Type: GrantFiled: July 13, 2020Date of Patent: September 27, 2022Assignee: Renesas Electronics CorporationInventor: Takashi Tonegawa
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Patent number: 11081454Abstract: Reliability of a semiconductor device having a plated layer formed on an electrode pad is improved. The method of manufacturing the semiconductor device includes a step for forming the plated layer on the electrode pad by moving the semiconductor wafer at a second speed, in a nickel-plating solution, after moving the semiconductor wafer at a first speed higher than the second speed. After moving the semiconductor wafer at the first speed, the semiconductor wafer is moved at the second speed without bringing the semiconductor wafer out from the nickel-plating solution.Type: GrantFiled: November 18, 2019Date of Patent: August 3, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Takashi Tonegawa
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Publication number: 20210225789Abstract: To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.Type: ApplicationFiled: April 8, 2021Publication date: July 22, 2021Inventors: Takashi TONEGAWA, Hiroshi INAGAWA
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Publication number: 20200343207Abstract: A method of manufacturing a semiconductor device includes forming an interlayer insulating film over a main surface of a semiconductor substrate, forming a first conductive film pattern for a first pad and a second conductive film pattern for a second pad over the interlayer insulating film, forming an insulating film over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns, forming a first opening portion for the first pad, the first opening portion exposing a portion of the first conductive film pattern, and a second opening portion for the second pad, the second opening portion exposing a portion of the second conductive film pattern, in the insulating film, and forming a first plated layer by plating over the portion of the first conductive film pattern exposed in the first opening portion, and a second plated layer.Type: ApplicationFiled: July 13, 2020Publication date: October 29, 2020Inventor: Takashi TONEGAWA
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Publication number: 20200203496Abstract: Reliability of a semiconductor device having a plated layer formed on an electrode pad is improved. The method of manufacturing the semiconductor device includes a step for forming the plated layer on the electrode pad by moving the semiconductor wafer at a second speed, in a nickel-plating solution, after moving the semiconductor wafer at a first speed higher than the second speed. After moving the semiconductor wafer at the first speed, the semiconductor wafer is moved at the second speed without bringing the semiconductor wafer out from the nickel-plating solution.Type: ApplicationFiled: November 18, 2019Publication date: June 25, 2020Inventor: Takashi TONEGAWA
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Patent number: 10504861Abstract: A semiconductor device and a method for manufacturing the semiconductor device which ensure improved reliability, permit further miniaturization, and suppress the increase in manufacturing cost. The semiconductor device includes: a pad electrode formed in the uppermost wiring layer of a multilayer wiring layer formed over a semiconductor substrate; a surface protective film formed in a manner to cover the pad electrode; an opening made in the surface protective film in a manner to expose the pad electrode partially; and a conductive layer formed over the pad electrode exposed at the bottom of the opening. The thickness of the conductive layer formed over the pad electrode is smaller than the thickness of the surface protective film formed over the pad electrode.Type: GrantFiled: May 24, 2018Date of Patent: December 10, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Moriyama, Takashi Tonegawa
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Publication number: 20190067225Abstract: To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.Type: ApplicationFiled: July 6, 2018Publication date: February 28, 2019Inventors: Takashi Tonegawa, Hiroshi Inagawa
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Publication number: 20190006300Abstract: A semiconductor device and a method for manufacturing the semiconductor device which ensure improved reliability, permit further miniaturization, and suppress the increase in manufacturing cost. The semiconductor device includes: a pad electrode formed in the uppermost wiring layer of a multilayer wiring layer formed over a semiconductor substrate; a surface protective film formed in a manner to cover the pad electrode; an opening made in the surface protective film in a manner to expose the pad electrode partially; and a conductive layer formed over the pad electrode exposed at the bottom of the opening. The thickness of the conductive layer formed over the pad electrode is smaller than the thickness of the surface protective film formed over the pad electrode.Type: ApplicationFiled: May 24, 2018Publication date: January 3, 2019Applicant: Renesas Electronics CorporationInventors: Takashi MORIYAMA, Takashi TONEGAWA
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Patent number: 10121958Abstract: An object is to prevent a short failure in magnetic tunnel junction and thereby suppress a semiconductor device having a magnetic memory cell from having deteriorated reliability. First, a data reference layer and a cap layer are patterned. After formation of an oxygen-free first insulating film on their side walls, a base layer, a data recording layer, and a tunnel barrier layer are patterned. During patterning of the base layer, data recording layer, and tunnel barrier layer, adhesion of a metal substance of the data reference layer and the cap layer to the side wall of the tunnel barrier layer can be prevented because the data reference layer and the cap layer are covered by the first insulating film.Type: GrantFiled: March 4, 2016Date of Patent: November 6, 2018Assignee: Renesas Electronics CorporationInventors: Takashi Tonegawa, Keiji Sakamoto
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Publication number: 20180138136Abstract: An insulating film is formed such that the insulating film covers a source electrode and a gate electrode, and an opening portion exposing a portion of the source electrode and an opening portion exposing a portion of the gate electrode are formed in the insulating film. A plated layer is formed over the source electrode exposed in the opening portion, and a plated layer is formed over the gate electrode exposed in the opening portion. A source pad is formed of the portion of the source electrode exposed in the opening portion, and the plated layer, and a gate pad is formed of the portion of the gate electrode exposed in the opening portion, and the plated layer. An area of the opening portion for the gate pad is smaller than an area of the opening portion for the source pad, and a thickness of the plated layer over the gate electrode is greater than a thickness of the plated layer over the source electrode.Type: ApplicationFiled: October 19, 2017Publication date: May 17, 2018Inventor: Takashi TONEGAWA
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Patent number: 9922928Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film provided over an interconnection and having an opening, and a plating film provided in the opening. A slit is provided in a side face of the opening, and the plating film is also disposed in the slit. Thus, the slit is provided in the side face of the opening, and the plating film is also grown in the slit. This results in a long penetration path of a plating solution during subsequent formation of the plating film. Hence, a corroded portion is less likely to be formed in the interconnection (pad region). Even if the corroded portion is formed, a portion of the slit is corroded prior to the interconnection (pad region) at a sacrifice, making it possible to suppress expansion of the corroded portion into the interconnection (pad region).Type: GrantFiled: July 23, 2016Date of Patent: March 20, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Takashi Tonegawa
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Publication number: 20170092605Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film provided over an interconnection and having an opening, and a plating film provided in the opening. A slit is provided in a side face of the opening, and the plating film is also disposed in the slit. Thus, the slit is provided in the side face of the opening, and the plating film is also grown in the slit. This results in a long penetration path of a plating solution during subsequent formation of the plating film. Hence, a corroded portion is less likely to be formed in the interconnection (pad region). Even if the corroded portion is formed, a portion of the slit is corroded prior to the interconnection (pad region) at a sacrifice, making it possible to suppress expansion of the corroded portion into the interconnection (pad region).Type: ApplicationFiled: July 23, 2016Publication date: March 30, 2017Inventor: Takashi TONEGAWA
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Publication number: 20160284980Abstract: An object is to prevent a short failure in magnetic tunnel junction and thereby suppress a semiconductor device having a magnetic memory cell from having deteriorated reliability. First, a data reference layer and a cap layer are patterned. After formation of an oxygen-free first insulating film on their side walls, a base layer, a data recording layer, and a tunnel barrier layer are patterned. During patterning of the base layer, data recording layer, and tunnel barrier layer, adhesion of a metal substance of the data reference layer and the cap layer to the side wall of the tunnel barrier layer can be prevented because the data reference layer and the cap layer are covered by the first insulating film.Type: ApplicationFiled: March 4, 2016Publication date: September 29, 2016Applicant: Renesas Electronics CorporationInventors: Takashi TONEGAWA, Keiji SAKAMOTO
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Publication number: 20160064654Abstract: The performances of a semiconductor device are improved. A semiconductor device has a conductive film formed above a semiconductor substrate, a first ferromagnetic film formed over the conductive film, an insulation film formed over the first ferromagnetic film, and a second ferromagnetic film formed over the insulation film. The first ferromagnetic film, the insulation film, and the second ferromagnetic film form a tunnel magnetoresistive effect element. The conductive film is formed of a metal nitride. The first ferromagnetic film contains cobalt, iron, and boron. The insulation film contains magnesium oxide.Type: ApplicationFiled: August 18, 2015Publication date: March 3, 2016Inventors: Takashi Tonegawa, Eiji Kariyada, Takayasu Kazamatsuri
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Patent number: 8435862Abstract: The method of manufacturing a semiconductor device comprises forming a metal film over silicon regions and insulating films; performing a first heat treatment under an oxygen atmosphere containing oxygen as a main ingredient, to form a first silicide film in the silicon region by reacting the metal film and the silicon region, and to simultaneously form a metal oxide by oxidizing the entire surface of the metal film from the surface side thereof; and selectively removing the metal oxide and the unreacted metal film using a chemical.Type: GrantFiled: March 23, 2011Date of Patent: May 7, 2013Assignee: Renesas Electronics CorporationInventors: Takashi Tonegawa, Tomotake Morita, Norihiko Matsuzaka
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Publication number: 20110237074Abstract: The method of manufacturing a semiconductor device comprises forming a metal film over silicon regions and insulating films; performing a first heat treatment under an oxygen atmosphere containing oxygen as a main ingredient, to form a first silicide film in the silicon region by reacting the metal film and the silicon region, and to simultaneously form a metal oxide by oxidizing the entire surface of the metal film from the surface side thereof; and selectively removing the metal oxide and the unreacted metal film using a chemical.Type: ApplicationFiled: March 23, 2011Publication date: September 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: TAKASHI TONEGAWA, TOMOTAKE MORITA, NORIHIKO MATSUZAKA
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Patent number: 7563705Abstract: A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a plasma treatment is performed after the via hole is formed and before the barrier metal is deposited, using a He/H2 gas capable of replacing groups (methyl groups) made of organic constituents and covering the surface of the exposed organic low dielectric film (MSQ) with hydrogen, or a He gas capable decomposing the groups (methyl groups) without removing organic low dielectric molecules. As a result, the surface of the low dielectric film (MSQ) is reformed to be hydrophilic and adhesion to the barrier metal is hence improved, thereby making it possible to prevent the occurrence of separation of the barrier metal and scratches.Type: GrantFiled: February 23, 2006Date of Patent: July 21, 2009Assignee: NEC Electronics CorporationInventors: Takashi Tonegawa, Koji Arita, Tatsuya Usami, Noboru Morita, Koichi Ohto, Yoichi Sasaki, Sadayuki Ohnishi, Ryohei Kitao