Patents by Inventor Takashi Tonegawa

Takashi Tonegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230411323
    Abstract: A dielectric layer has a first opening exposing a surface of a first conductive layer and a second opening exposing a surface of a second conductive layer and having an opening area smaller than an opening area of the first opening. A material of the surface of the second conductive layer exposed from the second opening is different from a material of the surface of the first conductive layer exposed from the first opening, and includes aluminum.
    Type: Application
    Filed: March 23, 2023
    Publication date: December 21, 2023
    Inventors: Etsuko WATANABE, Takashi TONEGAWA
  • Patent number: 11652072
    Abstract: To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: May 16, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Tonegawa, Hiroshi Inagawa
  • Publication number: 20230111921
    Abstract: First conductive layer is connected to an impurity region which is a source region or an emitter region. A first conductive layer having an emitter pad and a second conductive layer having a Kelvin emitter pad and a relay pad are separated. A plane occupied area of the Kelvin emitter pad is smaller than a plane occupied area of the emitter pad.
    Type: Application
    Filed: August 11, 2022
    Publication date: April 13, 2023
    Inventor: Takashi TONEGAWA
  • Patent number: 11456265
    Abstract: A method of manufacturing a semiconductor device includes forming an interlayer insulating film over a main surface of a semiconductor substrate, forming a first conductive film pattern for a first pad and a second conductive film pattern for a second pad over the interlayer insulating film, forming an insulating film over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns, forming a first opening portion for the first pad, the first opening portion exposing a portion of the first conductive film pattern, and a second opening portion for the second pad, the second opening portion exposing a portion of the second conductive film pattern, in the insulating film, and forming a first plated layer by plating over the portion of the first conductive film pattern exposed in the first opening portion, and a second plated layer.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: September 27, 2022
    Assignee: Renesas Electronics Corporation
    Inventor: Takashi Tonegawa
  • Patent number: 11081454
    Abstract: Reliability of a semiconductor device having a plated layer formed on an electrode pad is improved. The method of manufacturing the semiconductor device includes a step for forming the plated layer on the electrode pad by moving the semiconductor wafer at a second speed, in a nickel-plating solution, after moving the semiconductor wafer at a first speed higher than the second speed. After moving the semiconductor wafer at the first speed, the semiconductor wafer is moved at the second speed without bringing the semiconductor wafer out from the nickel-plating solution.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Tonegawa
  • Publication number: 20210225789
    Abstract: To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.
    Type: Application
    Filed: April 8, 2021
    Publication date: July 22, 2021
    Inventors: Takashi TONEGAWA, Hiroshi INAGAWA
  • Publication number: 20200343207
    Abstract: A method of manufacturing a semiconductor device includes forming an interlayer insulating film over a main surface of a semiconductor substrate, forming a first conductive film pattern for a first pad and a second conductive film pattern for a second pad over the interlayer insulating film, forming an insulating film over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns, forming a first opening portion for the first pad, the first opening portion exposing a portion of the first conductive film pattern, and a second opening portion for the second pad, the second opening portion exposing a portion of the second conductive film pattern, in the insulating film, and forming a first plated layer by plating over the portion of the first conductive film pattern exposed in the first opening portion, and a second plated layer.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 29, 2020
    Inventor: Takashi TONEGAWA
  • Publication number: 20200203496
    Abstract: Reliability of a semiconductor device having a plated layer formed on an electrode pad is improved. The method of manufacturing the semiconductor device includes a step for forming the plated layer on the electrode pad by moving the semiconductor wafer at a second speed, in a nickel-plating solution, after moving the semiconductor wafer at a first speed higher than the second speed. After moving the semiconductor wafer at the first speed, the semiconductor wafer is moved at the second speed without bringing the semiconductor wafer out from the nickel-plating solution.
    Type: Application
    Filed: November 18, 2019
    Publication date: June 25, 2020
    Inventor: Takashi TONEGAWA
  • Patent number: 10504861
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device which ensure improved reliability, permit further miniaturization, and suppress the increase in manufacturing cost. The semiconductor device includes: a pad electrode formed in the uppermost wiring layer of a multilayer wiring layer formed over a semiconductor substrate; a surface protective film formed in a manner to cover the pad electrode; an opening made in the surface protective film in a manner to expose the pad electrode partially; and a conductive layer formed over the pad electrode exposed at the bottom of the opening. The thickness of the conductive layer formed over the pad electrode is smaller than the thickness of the surface protective film formed over the pad electrode.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: December 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Moriyama, Takashi Tonegawa
  • Publication number: 20190067225
    Abstract: To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.
    Type: Application
    Filed: July 6, 2018
    Publication date: February 28, 2019
    Inventors: Takashi Tonegawa, Hiroshi Inagawa
  • Publication number: 20190006300
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device which ensure improved reliability, permit further miniaturization, and suppress the increase in manufacturing cost. The semiconductor device includes: a pad electrode formed in the uppermost wiring layer of a multilayer wiring layer formed over a semiconductor substrate; a surface protective film formed in a manner to cover the pad electrode; an opening made in the surface protective film in a manner to expose the pad electrode partially; and a conductive layer formed over the pad electrode exposed at the bottom of the opening. The thickness of the conductive layer formed over the pad electrode is smaller than the thickness of the surface protective film formed over the pad electrode.
    Type: Application
    Filed: May 24, 2018
    Publication date: January 3, 2019
    Applicant: Renesas Electronics Corporation
    Inventors: Takashi MORIYAMA, Takashi TONEGAWA
  • Patent number: 10121958
    Abstract: An object is to prevent a short failure in magnetic tunnel junction and thereby suppress a semiconductor device having a magnetic memory cell from having deteriorated reliability. First, a data reference layer and a cap layer are patterned. After formation of an oxygen-free first insulating film on their side walls, a base layer, a data recording layer, and a tunnel barrier layer are patterned. During patterning of the base layer, data recording layer, and tunnel barrier layer, adhesion of a metal substance of the data reference layer and the cap layer to the side wall of the tunnel barrier layer can be prevented because the data reference layer and the cap layer are covered by the first insulating film.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Tonegawa, Keiji Sakamoto
  • Publication number: 20180138136
    Abstract: An insulating film is formed such that the insulating film covers a source electrode and a gate electrode, and an opening portion exposing a portion of the source electrode and an opening portion exposing a portion of the gate electrode are formed in the insulating film. A plated layer is formed over the source electrode exposed in the opening portion, and a plated layer is formed over the gate electrode exposed in the opening portion. A source pad is formed of the portion of the source electrode exposed in the opening portion, and the plated layer, and a gate pad is formed of the portion of the gate electrode exposed in the opening portion, and the plated layer. An area of the opening portion for the gate pad is smaller than an area of the opening portion for the source pad, and a thickness of the plated layer over the gate electrode is greater than a thickness of the plated layer over the source electrode.
    Type: Application
    Filed: October 19, 2017
    Publication date: May 17, 2018
    Inventor: Takashi TONEGAWA
  • Patent number: 9922928
    Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film provided over an interconnection and having an opening, and a plating film provided in the opening. A slit is provided in a side face of the opening, and the plating film is also disposed in the slit. Thus, the slit is provided in the side face of the opening, and the plating film is also grown in the slit. This results in a long penetration path of a plating solution during subsequent formation of the plating film. Hence, a corroded portion is less likely to be formed in the interconnection (pad region). Even if the corroded portion is formed, a portion of the slit is corroded prior to the interconnection (pad region) at a sacrifice, making it possible to suppress expansion of the corroded portion into the interconnection (pad region).
    Type: Grant
    Filed: July 23, 2016
    Date of Patent: March 20, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Tonegawa
  • Publication number: 20170092605
    Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film provided over an interconnection and having an opening, and a plating film provided in the opening. A slit is provided in a side face of the opening, and the plating film is also disposed in the slit. Thus, the slit is provided in the side face of the opening, and the plating film is also grown in the slit. This results in a long penetration path of a plating solution during subsequent formation of the plating film. Hence, a corroded portion is less likely to be formed in the interconnection (pad region). Even if the corroded portion is formed, a portion of the slit is corroded prior to the interconnection (pad region) at a sacrifice, making it possible to suppress expansion of the corroded portion into the interconnection (pad region).
    Type: Application
    Filed: July 23, 2016
    Publication date: March 30, 2017
    Inventor: Takashi TONEGAWA
  • Publication number: 20160284980
    Abstract: An object is to prevent a short failure in magnetic tunnel junction and thereby suppress a semiconductor device having a magnetic memory cell from having deteriorated reliability. First, a data reference layer and a cap layer are patterned. After formation of an oxygen-free first insulating film on their side walls, a base layer, a data recording layer, and a tunnel barrier layer are patterned. During patterning of the base layer, data recording layer, and tunnel barrier layer, adhesion of a metal substance of the data reference layer and the cap layer to the side wall of the tunnel barrier layer can be prevented because the data reference layer and the cap layer are covered by the first insulating film.
    Type: Application
    Filed: March 4, 2016
    Publication date: September 29, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Takashi TONEGAWA, Keiji SAKAMOTO
  • Publication number: 20160064654
    Abstract: The performances of a semiconductor device are improved. A semiconductor device has a conductive film formed above a semiconductor substrate, a first ferromagnetic film formed over the conductive film, an insulation film formed over the first ferromagnetic film, and a second ferromagnetic film formed over the insulation film. The first ferromagnetic film, the insulation film, and the second ferromagnetic film form a tunnel magnetoresistive effect element. The conductive film is formed of a metal nitride. The first ferromagnetic film contains cobalt, iron, and boron. The insulation film contains magnesium oxide.
    Type: Application
    Filed: August 18, 2015
    Publication date: March 3, 2016
    Inventors: Takashi Tonegawa, Eiji Kariyada, Takayasu Kazamatsuri
  • Patent number: 8435862
    Abstract: The method of manufacturing a semiconductor device comprises forming a metal film over silicon regions and insulating films; performing a first heat treatment under an oxygen atmosphere containing oxygen as a main ingredient, to form a first silicide film in the silicon region by reacting the metal film and the silicon region, and to simultaneously form a metal oxide by oxidizing the entire surface of the metal film from the surface side thereof; and selectively removing the metal oxide and the unreacted metal film using a chemical.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: May 7, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Tonegawa, Tomotake Morita, Norihiko Matsuzaka
  • Publication number: 20110237074
    Abstract: The method of manufacturing a semiconductor device comprises forming a metal film over silicon regions and insulating films; performing a first heat treatment under an oxygen atmosphere containing oxygen as a main ingredient, to form a first silicide film in the silicon region by reacting the metal film and the silicon region, and to simultaneously form a metal oxide by oxidizing the entire surface of the metal film from the surface side thereof; and selectively removing the metal oxide and the unreacted metal film using a chemical.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 29, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: TAKASHI TONEGAWA, TOMOTAKE MORITA, NORIHIKO MATSUZAKA
  • Patent number: 7563705
    Abstract: A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a plasma treatment is performed after the via hole is formed and before the barrier metal is deposited, using a He/H2 gas capable of replacing groups (methyl groups) made of organic constituents and covering the surface of the exposed organic low dielectric film (MSQ) with hydrogen, or a He gas capable decomposing the groups (methyl groups) without removing organic low dielectric molecules. As a result, the surface of the low dielectric film (MSQ) is reformed to be hydrophilic and adhesion to the barrier metal is hence improved, thereby making it possible to prevent the occurrence of separation of the barrier metal and scratches.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: July 21, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Takashi Tonegawa, Koji Arita, Tatsuya Usami, Noboru Morita, Koichi Ohto, Yoichi Sasaki, Sadayuki Ohnishi, Ryohei Kitao