Abstract: A setting value is initially stored in a comparison and coincidence register. Thereafter, a value of a count signal is incremented in a base timer while resetting the value of the count signal to zero each time the value of the count signal reaches a prescribed value. A coincidence signal set to “1” is output from the comparison and coincidence register each time the setting value agrees with the value of the count signal, and a clock signal is produced in an RS flip-flop according to the coincidence signal. A data transmission is performed each time the coincidence signal is received in a transmission shift register. On a reception side, the clock signal is received, and the data is received according to the clock signal. Therefore, in cases where a desired setting value is stored in the comparison and coincidence register, the repetition period of the data transmission and reception can be freely changed.

Abstract: To enable the measurer to easily verify the parameter correction conditions, the correction conditions for the parameters measurable by the measurement device are concurrently displayed on the screen of the measurement device related to the ports used in the parameter measurement. The rows and columns are the receive ports and send ports. The symbol F and the symbol R indicate the type of calibration method applied to the parameters measured by the ports specified in the matrix.

Abstract: An electroacoustic transducer comprises a carrier portion, a diaphragm supported by the carrier portion, an electrode portion opposed to the diaphragm at a predetermined interval, and a housing accommodating the diaphragm and the electrode portion, wherein the carrier portion has a saucer-like shape, at the bottom surface of which a plurality of upstanding posts are provided, and wherein the upper surface of the periphery of the carrier portion and the upper end surfaces of the posts are in the same plane, the diaphragm is bonded to the surface of the periphery of the carrier portion and the end surfaces of the posts, and the electrode portion is fixed to the end surfaces of the posts which are covered by the diaphragm with spacers interposed therebetween.

Abstract: The object of the present invention is to provide an electroacoustic transducer characterized in that the desirable tension of a diaphragm is not changed, the interval between the diaphragm and the electrode portion can accurately be kept, the amplitude of the diaphragm in response to sound waves can be increased, and the influence of an external force can be reduced.

Abstract: To enable the measurer to easily verify the parameter correction conditions, the correction conditions for the parameters measurable by the measurement device are concurrently displayed on the screen of the measurement device related to the ports used in the parameter measurement. The rows and columns are the receive ports and send ports. The symbol F and the symbol R indicate the type of calibration method applied to the parameters measured by the ports specified in the matrix.

Abstract: A setting value is initially stored in a comparison and coincidence register. Thereafter, a value of a count signal is incremented in a base timer while resetting the value of the count signal to zero each time the value of the count signal reaches a prescribed value. A coincidence signal set to “1” is output from the comparison and coincidence register each time the setting value agrees with the value of the count signal, and a clock signal is produced in an RS flip-flop according to the coincidence signal. A data transmission is performed each time the coincidence signal is received in a transmission shift register. On a reception side, the clock signal is received, and the data is received according to the clock signal. Therefore, in cases where a desired setting value is stored in the comparison and coincidence register, the repetition period of the data transmission and reception can be freely changed.

Abstract: A microcomputer is realized having a built-in SIO which is able to correspond to a LAN which requires strict timing control and also correspond to a high speed serial communication. A counter supplies.a clock signal for data shift to an SIO register which performs serial-parallel conversion and vice versa. Two D flip-flop circuits detect the rise of an SRDY signal, an input signal expressing the start of transmission, and give the counter a reset signal.

Abstract: A wiring board for flip-chip-mounting in which a conductor layer is provided in a portion under the semiconductor element-mounting surface of the ceramic insulating board, the electrically conducting layer being electrically independent from the wiring pattern that is flip-chip-connected. The insulating board is effectively suppressed from deforming such as from warping or undulating. In particular, the semiconductor element-mounting surface exhibits a high degree of flatness. Therefore, the wiring board exhibits a high junction reliability at the flip-chip-connected portions, and is very useful as a semiconductor package or as a hybrid integrated circuit that is used in various electronic devices being mounted on the vehicles.

Abstract: Via portions are formed in a first green sheet for a first layer of a laminated substrate. Then, conductive lands are formed on a surface of the first green sheet and a wiring pattern is formed on a back face of the first green sheet to be connected to the conductive lands through the via portions. The thus formed first green sheet is joined to a second green sheet having via portions therein so that the wiring pattern of the first green sheet contacts the via portions of the second green sheet. In this case, by forming the wiring pattern on the back face of the first green sheet, lamination slippage of the wiring pattern caused by lamination of the first and second green sheets can be prevented.

Abstract: An internal clock synchronizing circuit capable of solving a problem involved in a conventional high speed microcomputer system in that it takes a long time to establish clock synchronization between system component circuits of the microcomputer system. The internal clock synchronizing circuit includes a clock generator for generating an internal clock signal by dividing an original clock signal; a clock comparator for comparing the internal clock signal with a reference clock signal; a compared result holding circuit for holding, in synchronism with the original clock signal, a compared result signal output from the clock comparator; and a clock switching circuit for switching supply of the original clock signal to the clock generator in response to the compared result signal held in the compared result holding circuit.

Abstract: A package body holding an acceleration sensor circuit therein has signal electrodes and four dummy electrodes insulated from the signal electrode on a mounted surface thereof. The signal electrodes are electrically connected to the sensor circuit element. The mounted surface of the package body has chamfered portions on verge portions thereof, and auxiliary electrodes are formed on the chamfered portions to be integrally connected to the signal electrodes. The thus constructed package body is mounted on a circuit board by a reflow method using a solder paste so that the signal, dummy, and auxiliary electrodes are connected to a wiring pattern on the circuit board through solder portions. In this process, the solder paste on the dummy electrodes in a fused state generate an internal pressure to retain a clearance between the package body and the circuit board.

Abstract: A microcomputer or a one-chip computer has address pins and data pins provided separately, and when a specified control signal is provided, the address pins act as multiplex pins for address and data signals. Further, a combination of bits for address signals and bits for data signals to be provided to the multiplex pins are changed according to a width of an external bus. For example, the data bits D.sub.i are combined with the address bits A.sub.i, as used previously. Further, the data bits D.sub.i-1 are combined with the address bits A.sub.i by shifting by one bit with respect to the address bits. One of the two types of the combination can be selected. If the microcomputer has 16-bit address pins, it can be connected to 8-bit memories having independent address and data pins, while it can also be connected to 8-bit peripherals having multiplex pins without using an external circuit for separating address and data signals.

Abstract: A power converter has two switched capacitor circuits each including at least a plurality of sets of capacitors and switching elements, first of which circuits is provided for supplying a DC power to a load while second of which accumulates a power in a period receiving a higher input voltage, and the first switched capacitor circuit being made to receive, in a period receiving a lower input voltage, a power supplied from a DC power source and also the power supplied from the second switched capacitor circuit for supplying to the load the DC power of a constant voltage, in which an input current collectively taken up by the two switched capacitor circuits is made similar in the waveform to the input voltage to eliminate any harmonics distortion of the current drawn from the source, for attaining the supply of the DC power of the constant voltage to the load, whereby the power converter is rendered not to require any large inductor to be capable of being minimized in size and restraining any noise radiation fr

Abstract: A DMA control system continuously grants permission to access the I/O device and memory to continue data transfer in a cycle steal mode when there is a continuous stream of DMA requests from a number of I/O devices by producing a logical sum of the DMA requests.

Abstract: A DMA transfer of 8-bit units and 16-bit units can be performed regardless of the proceeding direction of the address and whether the first address to be accessed is even or odd. In a conventional DMA transfer, the DMA control device required a function for selecting 8-bit configuration or 16-bit configuration of transfer data when the proceeding directions of addresses at the transfer source and transfer destination were different. The present invention reverses a determined result and indicates whether the first address to be transferred is even or odd, when the proceeding direction of the address is "reverse" and the data has a 16-bit configuration.

Abstract: A DMA controller interrupts data transfer as needed to transfer the bus use permit to the CPU and resumes data transfer when the CPU completes the memory use in the burst mode in which the predetermined number of words is transferred between the I/O device and the memory.

Abstract: In a normal state, a time counting process and a key input process are performed in accordance with an oscillation signal of 38.4 KHz generated by a crystal oscillator. In a data communication mode, a process for exchanging data with an external appliance is performed in accordance with a frequency-divided signal of the above oscillation signal and received data are stored in a memory simultaneously in a high speed process under control of an oscillation signal of 800 KHz generated by a CR oscillator. A power source circuit provides a high power source voltage, preventing all circuits from a defective operation while the high speed process is performed since the high speed process can decrease a power source voltage.

Abstract: A priority control system for determining a priority order of bus requests in an information processor includes a main group of first bus request sources; an auxiliary group of second bus request sources provided in one of the first bus request sources; and a sampling unit responsive to the bus use conditions to effect sampling to check if there is a bus request for either said main or said auxiliary group.