Takashi Yamasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A DMA transfer of 8-bit units and 16-bit units can be performed regardless of the proceeding direction of the address and whether the first address to be accessed is even or odd. In a conventional DMA transfer, the DMA control device required a function for selecting 8-bit configuration or 16-bit configuration of transfer data when the proceeding directions of addresses at the transfer source and transfer destination were different. The present invention reverses a determined result and indicates whether the first address to be transferred is even or odd, when the proceeding direction of the address is "reverse" and the data has a 16-bit configuration.
Abstract: A DMA controller interrupts data transfer as needed to transfer the bus use permit to the CPU and resumes data transfer when the CPU completes the memory use in the burst mode in which the predetermined number of words is transferred between the I/O device and the memory.
Abstract: In a normal state, a time counting process and a key input process are performed in accordance with an oscillation signal of 38.4 KHz generated by a crystal oscillator. In a data communication mode, a process for exchanging data with an external appliance is performed in accordance with a frequency-divided signal of the above oscillation signal and received data are stored in a memory simultaneously in a high speed process under control of an oscillation signal of 800 KHz generated by a CR oscillator. A power source circuit provides a high power source voltage, preventing all circuits from a defective operation while the high speed process is performed since the high speed process can decrease a power source voltage.
Abstract: A priority control system for determining a priority order of bus requests in an information processor includes a main group of first bus request sources; an auxiliary group of second bus request sources provided in one of the first bus request sources; and a sampling unit responsive to the bus use conditions to effect sampling to check if there is a bus request for either said main or said auxiliary group.