Patents by Inventor Takasumi Ohyanagi
Takasumi Ohyanagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7763504Abstract: A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.Type: GrantFiled: February 19, 2008Date of Patent: July 27, 2010Assignees: DENSO CORPORATION, Hitachi, Ltd.Inventors: Rajesh Kumar, Tsuyoshi Yamamoto, Hiroki Nakamura, Toshiyuki Morishita, Takasumi Ohyanagi, Atsuo Watanabe
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Patent number: 7663181Abstract: A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first conduction type formed on the semiconductor base, a source ohmic contact metal film in ohmic contact with the source region, trenches formed from the second surface of the semiconductor base, and a gate region of second conduction type formed along the trenches. The semiconductor device further includes a gate rise metal film in ohmic contact with the draw-out layer of the gate region on the bottom of the trenches and rising to the second surface of the semiconductor base, and a gate draw-out metal film connected to the gate rise metal film from the second surface of the semiconductor base.Type: GrantFiled: August 18, 2005Date of Patent: February 16, 2010Assignees: Hitachi, Ltd., Denso CorporationInventors: Takasumi Ohyanagi, Atsuo Watanabe, Toshio Sakakibara, Tsuyoshi Yamamoto, Hiroki Nakamura
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Publication number: 20080153216Abstract: A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.Type: ApplicationFiled: February 19, 2008Publication date: June 26, 2008Applicants: DENSO CORPORATION, HITACHI, LTD.Inventors: Rajesh Kumar, Tsuyoshi Yamamoto, Hiroki Nakamura, Toshiyuki Morishita, Takasumi Ohyanagi, Atsuo Watanabe
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Patent number: 7355207Abstract: A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.Type: GrantFiled: May 24, 2005Date of Patent: April 8, 2008Assignees: DENSO CORPORATION, Hitachi, Ltd.Inventors: Rajesh Kumar, Tsuyoshi Yamamoto, Hiroki Nakamura, Toshiyuki Morishita, Takasumi Ohyanagi, Atsuo Watanabe
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Patent number: 7335928Abstract: A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.Type: GrantFiled: May 25, 2007Date of Patent: February 26, 2008Assignees: Hitachi, Ltd., Denso CorporationInventors: Takasumi Ohyanagi, Atsuo Watanabe, Rajesh Kumar Malhan, Tsuyoshi Yamamoto, Toshiyuki Morishita
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Patent number: 7307313Abstract: A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.Type: GrantFiled: August 18, 2005Date of Patent: December 11, 2007Assignees: Hitachi, Ltd., Denso CorporationInventors: Takasumi Ohyanagi, Atsuo Watanabe, Toshio Sakakibara, Tsuyoshi Yamamoto, Hiroki Nakamura, Rajesh Kumar Malhan
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Publication number: 20070221924Abstract: A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.Type: ApplicationFiled: May 25, 2007Publication date: September 27, 2007Inventors: Takasumi Ohyanagi, Atsuo Watanabe, Rajesh Malhan, Tsuyoshi Yamamoto, Toshiyuki Morishita
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Patent number: 7230283Abstract: A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.Type: GrantFiled: May 27, 2005Date of Patent: June 12, 2007Assignees: Hitachi, Ltd., DENSO CorporationInventors: Takasumi Ohyanagi, Atsuo Watanabe, Rajesh Kumar Malhan, Tsuyoshi Yamamoto, Toshiyuki Morishita
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Patent number: 7067878Abstract: A MOS field effect transistor. A field relaxation layer of a gate overlap structure is disposed in contact with a drain region for the purpose of relaxation of the electric field by increasing a distance between the field relaxation layer and a high-density layer. The electric field relaxation can further be promoted because the equipotential lines are bent by a gate insulation film. A punch-through stopper layer of a gate overlap structure is disposed in contact with a source region for suppressing spreading of a depletion layer toward the source region. The length of a gate electrode can be realized in a miniaturized size.Type: GrantFiled: September 28, 2001Date of Patent: June 27, 2006Assignee: Hitachi, Ltd.Inventors: Takasumi Ohyanagi, Atsuo Watanabe
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Publication number: 20060076613Abstract: A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.Type: ApplicationFiled: August 18, 2005Publication date: April 13, 2006Inventors: Takasumi Ohyanagi, Atsuo Watanabe, Toshio Sakakibara, Tsuyoshi Yamamoto, Hiroki Nakamura, Rajesh Malhan
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Publication number: 20060071217Abstract: A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first conduction type formed on the semiconductor base, a source ohmic contact metal film in ohmic contact with the source region, trenches formed from the second surface of the semiconductor base, and a gate region of second conduction type formed along the trenches. The semiconductor device further includes a gate rise metal film in ohmic contact with the draw-out layer of the gate region on the bottom of the trenches and rising to the second surface of the semiconductor base, and a gate draw-out metal film connected to the gate rise metal film from the second surface of the semiconductor base.Type: ApplicationFiled: August 18, 2005Publication date: April 6, 2006Inventors: Takasumi Ohyanagi, Atsuo Watanabe, Toshio Sakakibara, Tsuyoshi Yamamoto, Hiroki Nakamura
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Publication number: 20060060884Abstract: A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.Type: ApplicationFiled: May 27, 2005Publication date: March 23, 2006Inventors: Takasumi Ohyanagi, Atsuo Watanabe, Rajesh Malhan, Tsuyoshi Yamamoto, Toshiyuki Morishita
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Publication number: 20050258454Abstract: A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.Type: ApplicationFiled: May 24, 2005Publication date: November 24, 2005Inventors: Rajesh Kumar, Tsuyoshi Yamamoto, Hiroki Nakamura, Toshiyuki Morishita, Takasumi Ohyanagi, Atsuo Watanabe
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Patent number: 6909155Abstract: An N-channel MOS field-effect transistor on an SOI substrate including a source electrode, drain and gate electrodes both disposed via a field oxide film, a gate oxide film, a high concentration P-type layer, a high concentration N-type layer contacting the source electrode and the gate oxide film, a high concentration N-type layer contacting the drain electrode, a p-body layer contacting the high concentration P-type and N-type layers and the gate oxide film. In this transistor, an N-type layer with a concentration higher than that of a drain region contacting the p-body layer constitutes a region covering at most 95% of the source-drain distance. Further, an N-type region having a concentration from 3×1016/cm3 to 1×1022/cm3 is provided near a buried oxide film under the drain electrode.Type: GrantFiled: March 20, 2002Date of Patent: June 21, 2005Assignee: Hitachi, Ltd.Inventors: Takasumi Ohyanagi, Atsuo Watanabe
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Patent number: 6885067Abstract: A power IC for an automobile engine control unit incorporating at least one semiconductor device comprising an N-channel insulated-gate filed-effect transistor formed on an SOI substrate, having an N-type layer having a concentration higher than a concentration of an N-type layer in contact with a p-body layer contacting a gate oxide film of the transistor. The high concentration N-type layer is formed in a region covering at most 95% of the source-drain distance between the p-body layer and a drain electrode of the transistor in the silicon substrate over an interface of a buried oxide film, the silicon substrate being in contact with both the field oxide film and the high concentration N-type layer contacting the drain electrode.Type: GrantFiled: March 4, 2004Date of Patent: April 26, 2005Assignee: Hitachi, Ltd.Inventors: Takasumi Ohyanagi, Atsuo Watanabe
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Publication number: 20040169251Abstract: A power IC for an automobile engine control unit incorporating at least one semiconductor device comprising an N-channel insulated-gate filed-effect transistor formed on an SOI substrate, having an N-type layer having a concentration higher than a concentration of an N-type layer in contact with a p-body layer contacting a gate oxide film of the transistor. The high concentration N-type layer is formed in a region covering at most 95% of the source-drain distance between the p-body layer and a drain electrode of the transistor in the silicon substrate over an interface of a buried oxide film, the silicon substrate being in contact with both the field oxide film and the high concentration N-type layer contacting the drain electrode.Type: ApplicationFiled: March 4, 2004Publication date: September 2, 2004Inventors: Takasumi Ohyanagi, Atsuo Watanabe
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Patent number: 6750513Abstract: An N-channel MOS field-effect transistor on an SOI substrate including a source electrode, drain and gate electrodes both disposed via a field oxide film, a gate oxide film, a high concentration P-type layer, a high concentration N-type layer contacting the source electrode and the gate oxide film, a high concentration N-type layer contacting the drain electrode, a p-body layer contacting the high concentration P-type and N-type layers and the gate oxide film. In this transistor, an N-type layer with a concentration higher than that of a drain region contacting the p-body layer constitutes a region covering at most 95% of the source-drain distance. Further, an N-type region having a concentration from 3×1016/cm3 to 1×1022/cm3 is provided near a buried oxide film under the drain electrode.Type: GrantFiled: March 24, 2003Date of Patent: June 15, 2004Assignee: Hitachi, Ltd.Inventors: Takasumi Ohyanagi, Atsuo Watanabe
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Patent number: 6657257Abstract: According to the present invention, there is provided an N-type insulated gate field effect transistor using an SOI substrate of which Si layer as a device formation area is N-type. The SOI substrate provided as the device formation area has the N-type semiconductor region, which has an impurity concentration higher than the impurity concentration of the device formation area, formed so that the N-type semiconductor region is contacted to a part of a gate insulating film and a field silicon oxide film formed between a source electrode and a drain electrode, and extends to be contacted to the N-type semiconductor diffusion layer contacted to the drain electrode. According to the above arrangement, the on-state breakdown can be remarkably improved.Type: GrantFiled: April 9, 2001Date of Patent: December 2, 2003Assignee: Hitachi, Ltd.Inventors: Takasumi Ohyanagi, Atsuo Watanabe
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Publication number: 20030160284Abstract: An N-channel MOS field-effect transistor on an SOI substrate including a source electrode, drain and gate electrodes both disposed via a field oxide film, a gate oxide film, a high concentration P-type layer, a high concentration N-type layer contacting the source electrode and the gate oxide film, a high concentration N-type layer contacting the drain electrode, a p-body layer contacting the high concentration P-type and N-type layers and the gate oxide film. In this transistor, an N-type layer with a concentration higher than that of a drain region contacting the p-body layer constitutes a region covering at most 95% of the source-drain distance. Further, an N-type region having a concentration from 3×1016/cm3 to 1×1022/cm3 is provided near a buried oxide film under the drain electrode.Type: ApplicationFiled: March 24, 2003Publication date: August 28, 2003Inventors: Takasumi Ohyanagi, Atsuo Watanabe
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Patent number: 6570240Abstract: In order to form a semiconductor device including a lateral bipolar transistor which is a match in the device performance for a vertical bipolar transistor, an electrically conductive film which is formed by filling a trench reaching a buried oxide film in an SOI substrate with an electrically conductive film is utilized for an emitter and/or a collector, whereby a bipolar transistor is formed through a simple process.Type: GrantFiled: August 29, 2000Date of Patent: May 27, 2003Assignee: Hitachi, Ltd.Inventors: Takasumi Ohyanagi, Atsuo Watanabe