Patents by Inventor Takatoshi Kameshima

Takatoshi Kameshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998369
    Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 4, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
  • Publication number: 20210104571
    Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.
    Type: Application
    Filed: March 23, 2018
    Publication date: April 8, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Reijiroh SHOHJI, Masaki HANEDA, Hiroshi HORIKOSHI, Minoru ISHIDA, Takatoshi KAMESHIMA, Ikue MITSUHASHI, Hideto HASHIGUCHI, Tadashi IIJIMA
  • Publication number: 20210104572
    Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line in another wiring layer.
    Type: Application
    Filed: March 23, 2018
    Publication date: April 8, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takatoshi KAMESHIMA, Hideto HASHIGUCHI, Ikue MITSUHASHI, Hiroshi HORIKOSHI, Reijiroh SHOHJI, Minoru ISHIDA, Tadashi IIJIMA, Masaki HANEDA
  • Publication number: 20210104570
    Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance.
    Type: Application
    Filed: March 23, 2018
    Publication date: April 8, 2021
    Inventors: IKUE MITSUHASHI, REIJIROH SHOHJI, MINORU ISHIDA, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, HIROSHI HORIKOSHI, MASAKI HANEDA
  • Publication number: 20200243591
    Abstract: [Object] To further improve performance of a solid-state imaging device. [Solution] There is provided a solid-state imaging device including: a first substrate; a second substrate; and a third substrate that are stacked in this order. The first substrate includes a first semiconductor substrate and a first multi-layered wiring layer stacked on the first semiconductor substrate. The first semiconductor substrate has a pixel unit formed thereon. The pixel unit has pixels arranged thereon. The second substrate includes a second semiconductor substrate and a second multi-layered wiring layer stacked on the second semiconductor substrate. The second semiconductor substrate has a circuit formed thereon. The circuit has a predetermined function. The third substrate includes a third semiconductor substrate and a third multi-layered wiring layer stacked on the third semiconductor substrate. The third semiconductor substrate has a circuit formed thereon. The circuit has a predetermined function.
    Type: Application
    Filed: March 23, 2018
    Publication date: July 30, 2020
    Inventors: TADASHI IIJIMA, TAKATOSHI KAMESHIMA, IKUE MITSUHASHI, HIROSHI HORIKOSHI, HIDETO HASHIGUCHI, REIJIROH SHOHJI, MINORU ISHIDA, MASAKI HANEDA
  • Publication number: 20200105814
    Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.
    Type: Application
    Filed: March 23, 2018
    Publication date: April 2, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hideto HASHIGUCHI, Reijiroh SHOHJI, Hiroshi HORIKOSHI, Ikue MITSUHASHI, Tadashi IIJIMA, Takatoshi KAMESHIMA, Minoru ISHIDA, Masaki HANEDA
  • Publication number: 20200105813
    Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.
    Type: Application
    Filed: March 23, 2018
    Publication date: April 2, 2020
    Inventors: HIDETO HASHIGUCHI, REIJIROH SHOHJI, HIROSHI HORIKOSHI, IKUE MITSUHASHI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, MINORU ISHIDA, MASAKI HANEDA
  • Publication number: 20200098815
    Abstract: [Object] To further improve performance of a solid-state imaging device.
    Type: Application
    Filed: March 23, 2018
    Publication date: March 26, 2020
    Inventors: TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, IKUE MITSUHASHI, HIROSHI HORIKOSHI, REIJIROH SHOHJI, MINORU ISHIDA, TADASHI IIJIMA, MASAKI HANEDA
  • Publication number: 20200091217
    Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together with the first multi-layered wiring layer and the second semiconductor substrate opposed to each other.
    Type: Application
    Filed: March 23, 2018
    Publication date: March 19, 2020
    Inventors: HIROSHI HORIKOSHI, MINORU ISHIDA, REIJIROH SHOHJI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, HIDETO HASHIGUCHI, IKUE MITSUHASHI, MASAKI HANEDA
  • Publication number: 20200035630
    Abstract: The present disclosure relates to a semiconductor device, a manufacturing method, and an electronic device designed to suppress the occurrence of Cu pumping. A semiconductor device includes: a Cu electrode pad serving as a bonding surface for bonding a plurality of semiconductor members together; and an electrode via, the electrode via being a connection member that connects the Cu electrode pad to a lower-layer metal. The Cu electrode pad is formed in a location displaced from the electrode via. The present disclosure can be applied to, for example, a multilayer solid-state imaging device, such as a CMOS device.
    Type: Application
    Filed: October 5, 2017
    Publication date: January 30, 2020
    Inventor: TAKATOSHI KAMESHIMA
  • Patent number: 9224879
    Abstract: There is provided a semiconductor device including a substrate made from a semiconductor material, and layers that are made from plural kinds of materials and formed over the substrate. An opening portion that is formed to penetrate at least a layer formed as an insulating film among the layers formed over the substrate and expose a surface of an electrode pad is filled with aluminum or an aluminum alloy.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: December 29, 2015
    Assignee: Sony Corporation
    Inventor: Takatoshi Kameshima
  • Patent number: 8759222
    Abstract: Disclosed herein is a method for fabrication of semiconductor device involving a first step of coating the substrate with a double-layered insulating film in laminate structure having the skeletal structure of inorganic material and a second step of etching the upper layer of the insulating film as far as the lower layer of the insulating film. In the method for fabrication of semiconductor device, the first step is carried out in such a way that the skeletal structure is incorporated with a pore-forming material of hydrocarbon compound so that one layer of the insulating film contains more carbon than the other layer of the insulating film.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: June 24, 2014
    Assignee: Sony Corporation
    Inventors: Tsutomu Shimayama, Takatoshi Kameshima, Masaki Okamoto
  • Publication number: 20140054739
    Abstract: There is provided a semiconductor device including a substrate made from a semiconductor material, and layers that are made from plural kinds of materials and formed over the substrate. An opening portion that is formed to penetrate at least a layer formed as an insulating film among the layers formed over the substrate and expose a surface of an electrode pad is filled with aluminum or an aluminum alloy.
    Type: Application
    Filed: July 19, 2013
    Publication date: February 27, 2014
    Inventor: Takatoshi Kameshima
  • Patent number: 7897205
    Abstract: A film forming method is characterized in that the method is provided with a step of introducing a processing gas including inorganic silane gas into a processing chamber, in which a mounting table composed of ceramics including a metal oxide is arranged, and precoating an inner wall of the processing chamber including a surface of the mounting table with a silicon-containing nonmetal thin film; a step of mounting a substrate to be processed on the mounting table precoated with the nonmetal thin film; and a step of introducing a processing gas including organic silane gas into the processing chamber, and forming a silicon-containing nonmetal thin film on a surface of the substrate mounted on the mounting table.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: March 1, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Takatoshi Kameshima, Kohei Kawamura, Yasuo Kobayashi
  • Patent number: 7803705
    Abstract: A dielectric film (91) made of CF is deposited on a substrate. A protective layer comprising an SiCN film (93) is formed on the dielectric film (91). A film (94) serving as a hardmask made of SiCO is deposited on the protective layer by a plasma containing active species of silicon, carbon, and oxygen. When the protective layer is formed, an SiC film (92) is deposited on the dielectric film (91) by a plasma containing active species of silicon and carbon, and thereafter the SiCN film (93) is deposited on the SiC film (92) by a plasma containing active species of silicon, carbon, and nitrogen.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: September 28, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Yasuo Kobayashi, Kenichi Nishizawa, Takatoshi Kameshima, Takaaki Matsuoka
  • Patent number: 7602061
    Abstract: Disclosed herein is a semiconductor device including: an insulating film configured to be provided on a substrate and be porosified through decomposition and removal of a pore-forming material; a covering insulating film configured to be provided on the insulating film; and conductive layer patterns configured to be provided in the covering insulating film and the insulating film and reach the substrate, wherein the insulating film includes a non-porous region in which the pore-forming material remains.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: October 13, 2009
    Assignee: Sony Corporation
    Inventors: Yoshihisa Kagawa, Tsutomu Shimayama, Takatoshi Kameshima
  • Publication number: 20090061092
    Abstract: A film forming method is characterized in that the method is provided with a step of introducing a processing gas including inorganic silane gas into a processing chamber, in which a mounting table composed of ceramics including a metal oxide is arranged, and precoating an inner wall of the processing chamber including a surface of the mounting table with a silicon-containing nonmetal thin film; a step of mounting a substrate to be processed on the mounting table precoated with the nonmetal thin film; and a step of introducing a processing gas including organic silane gas into the processing chamber, and forming a silicon-containing nonmetal thin film on a surface of the substrate mounted on the mounting table.
    Type: Application
    Filed: April 7, 2006
    Publication date: March 5, 2009
    Applicant: Tokyo Electron Limited
    Inventors: Takatoshi Kameshima, Kohei Kawamura, Yasuo Kobayashi
  • Publication number: 20080254631
    Abstract: Disclosed herein is a method for fabrication of semiconductor device involving a first step of coating the substrate with a double-layered insulating film in laminate structure having the skeletal structure of inorganic material and a second step of etching the upper layer of the insulating film as far as the lower layer of the insulating film. In the method for fabrication of semiconductor device, the first step is carried out in such a way that the skeletal structure is incorporated with a pore-forming material of hydrocarbon compound so that one layer of the insulating film contains more carbon than the other layer of the insulating film.
    Type: Application
    Filed: March 1, 2007
    Publication date: October 16, 2008
    Inventors: Tsutomu Shimayama, Takatoshi Kameshima, Masaki Okamoto
  • Publication number: 20080254641
    Abstract: A dielectric film (91) made of CF is deposited on a substrate. A protective layer comprising an SiCN film (93) is formed on the dielectric film (91). A film (94) serving as a hardmask made of SiCO is deposited on the protective layer by a plasma containing active species of silicon, carbon, and oxygen. When the protective layer is formed, an SiC film (92) is deposited on the dielectric film (91) by a plasma containing active species of silicon and carbon, and thereafter the SiCN film (93) is deposited on the SiC film (92) by a plasma containing active species of silicon, carbon, and nitrogen.
    Type: Application
    Filed: January 13, 2005
    Publication date: October 16, 2008
    Applicant: Tokyo Electron Limited
    Inventors: Yasuo Kobayashi, Kenichi Nishizawa, Takatoshi Kameshima, Takaaki Matsuoka
  • Publication number: 20080054454
    Abstract: Disclosed herein is a semiconductor device including: an insulating film configured to be provided on a substrate and be porosified through decomposition and removal of a pore-forming material; a covering insulating film configured to be provided on the insulating film; and conductive layer patterns configured to be provided in the covering insulating film and the insulating film and reach the substrate, wherein the insulating film includes a non-porous region in which the pore-forming material remains.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 6, 2008
    Applicant: SONY CORPORATION
    Inventors: Yoshihisa Kagawa, Tsutomu Shimayama, Takatoshi Kameshima