Patents by Inventor Takatoshi Yasui

Takatoshi Yasui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230307326
    Abstract: A semiconductor device includes an insulating substrate, a semiconductor element joined onto the insulating substrate with a first joining material interposed therebetween, a plurality of support wires that are provided between the semiconductor element and an electrode plate provided above the semiconductor element in contact with the semiconductor element and the electrode plate, and a second joining material that is provided on the semiconductor element and joins the semiconductor element and the electrode plate.
    Type: Application
    Filed: December 21, 2022
    Publication date: September 28, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventor: Takatoshi YASUI
  • Patent number: 10682792
    Abstract: The mold device according to the present invention is a mold device to resin-seal the semiconductor device including an insert electrode, and in the semiconductor device, the insert electrode is provided with an insert hole, a nut having a screw hole is disposed in the insert electrode so that the insert hole and the screw hole communicate with each other, the mold device includes a mold body into which resin is injected to resin-seal the semiconductor device, including a side of the insert electrode where the nut is disposed, and a rod-like member that is inserted into the insert hole, and the rod-like member is inserted into the screw hole of the nut through the insert hole of the insert electrode to draw the nut to the side of the insert electrode.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: June 16, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takatoshi Yasui, Yuki Hata, Shoji Saito, Katsuji Ando, Korehide Okamoto, Ryoji Murai
  • Patent number: 10651720
    Abstract: An object of the present invention is to synchronize PWM between individual phases of an IPM, so that the IPM has a simplified-scale circuit. An IPM according to the present invention includes a DC-DC converter including a multi-phase arm having a plurality of phase arms connected in parallel on a secondary side, a secondary-wire-voltage detection circuit configured to detect a secondary wire voltage in each phase arm of the DC-DC converter, and a synchronization-signal generation circuit configured to generate a synchronization signal in each phase arm on the basis of the behavior of the secondary wire voltage.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: May 12, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takatoshi Yasui, Takahiko Murakami, Akira Yamamoto, Yoshikazu Tsunoda
  • Publication number: 20190103802
    Abstract: An object of the present invention is to synchronize PWM between individual phases of an IPM, so that the IPM has a simplified-scale circuit. An IPM according to the present invention includes a DC-DC converter including a multi-phase arm having a plurality of phase arms connected in parallel on a secondary side, a secondary-wire-voltage detection circuit configured to detect a secondary wire voltage in each phase arm of the DC-DC converter, and a synchronization-signal generation circuit configured to generate a synchronization signal in each phase arm on the basis of the behavior of the secondary wire voltage.
    Type: Application
    Filed: May 25, 2016
    Publication date: April 4, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takatoshi YASUI, Takahiko MURAKAMI, Akira YAMAMOTO, Yoshikazu TSUNODA
  • Publication number: 20180147758
    Abstract: The mold device according to the present invention is a mold device to resin-seal the semiconductor device including an insert electrode, and in the semiconductor device, the insert electrode is provided with an insert hole, a nut having a screw hole is disposed in the insert electrode so that the insert hole and the screw hole communicate with each other, the mold device includes a mold body into which resin is injected to resin-seal the semiconductor device, including a side of the insert electrode where the nut is disposed, and a rod-like member that is inserted into the insert hole, and the rod-like member is inserted into the screw hole of the nut through the insert hole of the insert electrode to draw the nut to the side of the insert electrode.
    Type: Application
    Filed: July 30, 2015
    Publication date: May 31, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takatoshi YASUI, Yuki HATA, Shoji SAITO, Katsuji ANDO, Korehide OKAMOTO, Ryoji MURAl
  • Patent number: 7388401
    Abstract: An input/output circuit device includes a first transistor which is formed at a substrate, a first gate of which receives an input signal, one of a first source and drain of which is connected to a first power supply terminal, and the other of the first source and drain of which is connected to an internal node; and a second transistor which is formed at the substrate, a second gate of which is connected to a second power supply terminal, one of a second source and drain of which is connected to an input/output node, and the other of the second source and drain of which is connected to the internal node. The substrate of the second transistor has an electrically floating potential.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: June 17, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Takatoshi Yasui
  • Publication number: 20070008007
    Abstract: An input/output circuit device includes a first transistor which is formed at a substrate, a first gate of which receives an input signal, one of a first source and drain of which is connected to a first power supply terminal, and the other of the first source and drain of which is connected to an internal node; and a second transistor which is formed at the substrate, a second gate of which is connected to a second power supply terminal, one of a second source and drain of which is connected to an input/output node, and the other of the second source and drain of which is connected to the internal node. The substrate of the second transistor has an electrically floating potential.
    Type: Application
    Filed: May 19, 2006
    Publication date: January 11, 2007
    Inventor: Takatoshi Yasui
  • Patent number: 7042007
    Abstract: A single evaluation portion is formed by disposing a plurality of MIS transistors used for evaluation having substantially the same structure as that of an actually used MIS transistor. In the evaluation portion, the respective source regions, drain regions, and gate electrodes of the MIS transistors used for evaluation are electrically connected in common to a source pad, a drain pad, and a gate pad, respectively. If the effective gate width of the single evaluation portion exceeds a given value, variations in characteristics evaluated by the evaluation portion approach variations in the characteristics of the entire semiconductor device. The accuracy of evaluating the characteristics of the semiconductor device can thus be improved by using the evaluation portion.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: May 9, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takatoshi Yasui, Atsuhiro Kajiya
  • Publication number: 20050161745
    Abstract: An NMIS gate implantation layer is generated by a method in which mask data of a P-type well implantation layer are added to mask data obtained by subtracting mask data of an NMIS-SD implantation layer and PMIS-SD implantation layer from mask data of an N-type well implantation layer. In a CMOS device fabricating process, ions are implanted into a polysilicon film by using the NMIS gate implantation layer, resulting in reduction in the total numbers of PN junctions and non-doped regions in a gate polysilicon film.
    Type: Application
    Filed: January 5, 2005
    Publication date: July 28, 2005
    Inventors: Tokuhiko Tamaki, Hiromasa Fujimoto, Takatoshi Yasui, Takehiro Hirai
  • Publication number: 20040217462
    Abstract: A DRAM cell transistor formed on a silicon substrate comprises a first BPSG film, a silicon oxide film as a supporting film laid thereover, a storage node including a contact portion filling a contact hole extended through the silicon oxide film and the first BPSG film, an oxidized silicon nitride film as a capacitor insulating film, and a plate electrode. There may be further provided a second BPSG film thereover. Even if the first BPSG film at a lower level is caused to reflow by a process for oxidizing the silicon nitride film for formation of the oxidized silicon nitride film as the capacitor insulating film or a process for reflowing the second BPSG film, the silicon oxide film as the supporting film applies to the capacitor insulating film a stress against the deformation thereof and hence, the oxidized silicon nitride film free from wrinkle or cracks is provided as the capacitor insulating film.
    Type: Application
    Filed: March 15, 2004
    Publication date: November 4, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Toyokazu Fujii, Takatoshi Yasui
  • Publication number: 20040212016
    Abstract: A single evaluation portion is formed by disposing a plurality of MIS transistors used for evaluation having substantially the same structure as that of an actually used MIS transistor. In the evaluation portion, the respective source regions, drain regions, and gate electrodes of the MIS transistors used for evaluation are electrically connected in common to a source pad, a drain pad, and a gate pad, respectively. If the effective gate width of the single evaluation portion exceeds a given value, variations in characteristics evaluated by the evaluation portion approach variations in the characteristics of the entire semiconductor device. The accuracy of evaluating the characteristics of the semiconductor device can thus be improved by using the evaluation portion.
    Type: Application
    Filed: April 15, 2004
    Publication date: October 28, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD
    Inventors: Takatoshi Yasui, Atsuhiro Kajiya
  • Patent number: 6110775
    Abstract: A DRAM cell transistor formed on a silicon substrate comprises a first BPSG film, a silicon oxide film as a supporting film laid thereover, a storage node including a contact portion filling a contact hole extended through the silicon oxide film and the first BPSG film, an oxidized silicon nitride film as a capacitor insulating film, and a plate electrode. There may be further provided a second BPSG film thereover. Even if the first BPSG film at a lower level is caused to reflow by a process for oxidizing the silicon nitride film for formation of the oxidized silicon nitride film as the capacitor insulating film or a process for ref lowing the second BPSG film, the silicon oxide film as the supporting film applies to the capacitor insulating film a stress against the deformation thereof and hence, the oxidized silicon nitride film free from wrinkle or cracks is provided as the capacitor insulating film.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: August 29, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Toyokazu Fujii, Takatoshi Yasui
  • Patent number: 5786273
    Abstract: Formed in a second interlayer dielectric are a first contact hole and a second contact hole. The first and second contact holes each extend to a first-level interconnect line. Tungsten is formed on the entirety of a substrate to form a first plug, a second plug, and a tungsten layer. A silicon oxide layer is formed. Thereafter, a patterning process is carried out to form a second-level interconnect line which is connected with the first plug and a top protective layer, and the top of the second plug remains exposed. A sidewall is formed on the side surfaces of the second-level interconnect line and the top protective layer. Subsequently, a third-level interconnect line, which is connected with the exposed second plug, is formed. Such arrangement not only reduces the number of contact hole formation masks, it also cuts down the number of fabrication steps. Further, the aspect ratio of the second contact hole becomes lower thereby achieving highly reliable semiconductor devices.
    Type: Grant
    Filed: February 14, 1996
    Date of Patent: July 28, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshitaka Hibi, Takatoshi Yasui, Hisashi Ogawa, Susumu Akamatsu, Shunsuke Kugo
  • Patent number: 5314848
    Abstract: Described is a method for manufacturing semiconductor devices which includes a heat treating process for heating and cooling semiconductor substrates mounted on a boat at a predetermined pitch according to a predetermined temperature profile, in order to flatten the surface of each semiconductor substrate by reflowing an insulating film containing impurities, for example, a BPSG film formed on the substrate. In the heat treating process, one of the control factors which affects the formation of grains or particles due to the impurities contained in the insulating film is set so as to prevent the impurities from generating grains or particles during the heat treatment. Also disclosed is a method of preventing the generation of grains or particles by widening the pitch of the mounted substrates.
    Type: Grant
    Filed: September 24, 1991
    Date of Patent: May 24, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takatoshi Yasui, Chiaki Kudo, Ichiro Nakao, Toyokazu Fujii, Yuka Terai, Shinichi Imai, Hiroshi Yamamoto, Yasushi Naito
  • Patent number: 5047815
    Abstract: A semiconductor memory device includes a capacitor and an insulating separation area in a trench formed around a switching transistor, with a storage electrode of the capacitor being sandwiched between an upper and a lower cell plate electrode to reduce leakage current due to the parasitic MOS transistor effect in the trench sidewall along the channel in the switching transistor and leakage current due to the gate-controlled diode effect in the trench sidewall. Also, a method is disclosed for manufacturing such semiconductor memory device.
    Type: Grant
    Filed: August 14, 1989
    Date of Patent: September 10, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuo Yasuhira, Takatoshi Yasui, Kazuhiro Matsuyama, Hideyuki Iwata, Masanori Fukumoto