Abstract: According to one embodiment, a storage device includes a nonvolatile memory, a controller configured to copy data stored in a first page in a first block to a second page in a second block, and an ECC circuit. The controller reads data from a part of the first page by using an upper limit voltage and lower limit voltage, performs a direct copy operation in the nonvolatile memory without via the ECC circuit if the number of error cells having threshold voltages higher than the lower limit voltage and lower than or equal to the upper limit voltage is less than or equal to a specified value, and performs error correction by using the ECC circuit if the number of error cells exceeds the specified value.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory, a controller configured to copy data stored in a first page in a first block to a second page in a second block, and an ECC circuit. The controller reads data from a part of the first page by using an upper limit voltage and lower limit voltage, performs a direct copy operation in the nonvolatile memory without via the ECC circuit if the number of error cells having threshold voltages higher than the lower limit voltage and lower than or equal to the upper limit voltage is less than or equal to a specified value, and performs error correction by using the ECC circuit if the number of error cells exceeds the specified value.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and controller. The nonvolatile semiconductor storage device has a file system area including a file allocation table (FAT), a data write-once area including a plurality of clusters, and a management information area which stores a pointer indicating a rewrite inhibition area of the clusters. The controller reads the FAT from the file system area of the nonvolatile semiconductor storage device, and sets the pointer based on a cluster use status recorded in the FAT.

Abstract: A memory system includes a nonvolatile memory having a plurality of data blocks each of which is a unit of data erase and has a plurality of pages, each of the pages being a unit of data write, and a controller which checks whether or not the nonvolatile memory has been affected by power interruption at power-on time and, if the nonvolatile memory has been affected by power interruption, writes data to that first page in a first data block which has not been affected by power interruption.

Abstract: A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block.

Abstract: A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block.

Abstract: A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block.

Abstract: A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block.

Abstract: A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block.

Abstract: A system for authenticating a memory card including: a memory card host device including a plural area authentication module which judges whether the memory card has plural storage areas, and an area switching module which switches a storage area subject to access a different storage area from among plural storage areas; a memory card including plural storage areas, at least one internal register which retains a value indicating the number of storage areas, and a controller which transmits the value indicating the number of the storage areas to the memory card host device; and a bus which transmits and receives data between the memory card host device and the memory card.

Abstract: An apparatus for estimating a frequency of access to a storage device that includes a flash memory and a controller for controlling the flash memory includes interface. Data is written into the flash memory in units of a page and being erased from the flash memory in units of a block consisting of pages. The interface is supplied with an internal signal transferred between the flash memory and the controller, configured to recognize the internal signal, and outputs the internal signal as an input signal. An erasure sequence detection section outputs a detection signal when address data is followed by an erasure command requesting erasure of data in the block specified by the address data in the input signal. An address holding section holds address data in the internal signal, and outputs held address data as erasure address data when supplied with the detection signal.

Abstract: A memory system includes a nonvolatile memory having a plurality of data blocks each of which is a unit of data erase and has a plurality of pages, each of the pages being a unit of data write, and a controller which checks whether or not the nonvolatile memory has been affected by power interruption at power-on time and, if the nonvolatile memory has been affected by power interruption, writes data to that first page in a first data block which has not been affected by power interruption.

Abstract: A memory controller includes a host interface, a holding circuit and a control circuit. The memory controller controls a semiconductor memory. The semiconductor memory includes memory blocks. The host interface is connectable to a host apparatus and receivable of write data and an address. The holding circuit is capable of holding the address. The control circuit searches information indicating an existence of a parent directory from the write data, and holds the address in the holding circuit when the information is detected. The control circuit successively writes the write data to the same memory block when a new write access is made with respect to the same address as the address held in the holding circuit.

Abstract: A system for authenticating a memory card including: a memory card host device including a plural area authentication module which judges whether the memory card has plural storage areas, and an area switching module which switches a storage area subject to access a different storage area from among plural storage areas; a memory card including plural storage areas, at least one internal register which retains a value indicating the number of storage areas, and a controller which transmits the value indicating the number of the storage areas to the memory card host device; and a bus which transmits and receives data between the memory card host device and the memory card.

Abstract: A system for authenticating a memory card including: a memory card host device including a plural area authentication module which judges whether the memory card has plural storage areas, and an area switching module which switches a storage area subject to access a different storage area from among plural storage areas; a memory card including plural storage areas, at least one internal register which retains a value indicating the number of storage areas, and a controller which transmits the value indicating the number of the storage areas to the memory card host device; and a bus which transmits and receives data between the memory card host device and the memory card.

Abstract: A memory system includes a ferroelectric memory formed by arranging a plurality of memory cells having a ferroelectric capacitor and cell transistor, a flash EEPROM formed by arranging a plurality of memory cells having a floating gate and capable of electrically erasing and writing data, a control circuit configured to control the ferroelectric memory and flash EEPROM, and an interface circuit configured to communicate with the outside. The flash EEPROM stores data. The ferroelectric memory stores at least one of root information for storing the data, directory information, the file name of the data, the file size of the data, file allocation table information storing the storage location of the data, and the write completion time of the data.

Abstract: A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an erase command in a block in which the data to be erased is written, when the erase command is issued with respect to the nonvolatile semiconductor memory and a controlling unit configured to output initial-value data as data to be read in response to a data read command, when the data read command is issued with respect to the nonvolatile semiconductor memory, and then when an address range of the data to be read in response to the data read command is included in the address range set by the setting unit.

Abstract: An apparatus for estimating a frequency of access to a storage device that includes a flash memory and a controller for controlling the flash memory includes interface. Data is written into the flash memory in units of a page and being erased from the flash memory in units of a block consisting of pages. The interface is supplied with an internal signal transferred between the flash memory and the controller, configured to recognize the internal signal, and outputs the internal signal as an input signal. An erasure sequence detection section outputs a detection signal when address data is followed by an erasure command requesting erasure of data in the block specified by the address data in the input signal. An address holding section holds address data in the internal signal, and outputs held address data as erasure address data when supplied with the detection signal.

Abstract: A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block.

Abstract: A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an erase command in a block in which the data to be erased is written, when the erase command is issued with respect to the nonvolatile semiconductor memory and a controlling unit configured to output initial-value data as data to be read in response to a data read command, when the data read command is issued with respect to the nonvolatile semiconductor memory, and then when an address range of the data to be read in response to the data read command is included in the address range set by the setting unit.