Patents by Inventor Takaya Yamanaka

Takaya Yamanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200212066
    Abstract: A semiconductor memory device includes first and second wiring layers above a semiconductor substrate, a memory pillar extending through the first and second wiring layers, a first plug contacting the first wiring layer, a second plug contacting the second wiring layer, a first pillar adjacent to the first plug and extending through the first wiring layer, and a second pillar adjacent to the second plug and extending through the first and second wiring layers. The memory pillar includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer on a side surface of the second semiconductor layer. The distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Inventors: Yusuke NAKANISHI, Takaya YAMANAKA, Akira MATSUMURA
  • Publication number: 20200098790
    Abstract: A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Reiko KOMIYA, Tatsuo IZUMI, Takaya YAMANAKA, Takeshi NAGATOMO, Karin TAKAGI
  • Patent number: 10600803
    Abstract: A semiconductor memory device includes first and second wiring layers above a semiconductor substrate, a memory pillar extending through the first and second wiring layers, a first plug contacting the first wiring layer, a second plug contacting the second wiring layer, a first pillar adjacent to the first plug and extending through the first wiring layer, and a second pillar adjacent to the second plug and extending through the first and second wiring layers. The memory pillar includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer on a side surface of the second semiconductor layer. The distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: March 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Nakanishi, Takaya Yamanaka, Akira Matsumura
  • Patent number: 10586656
    Abstract: A pressure valve to be arranged in a seal member sealing a casing in which a capacitor element is housed, the pressure valve having a base end positioned within the case and a tip positioned outside the case. The pressure valve includes a tapered portion having a tapered shape. At the top portion of the tapered portion, there is formed a slit able to undergo a state change between a close-state and an open-state by elastic deformation. When the casing internal pressure is less than a certain value, the slit maintains the close-state. When the casing internal pressure has reached the certain value, the slit undergoes a state change to the open-state, whereby the inside and outside of the case communicate with each other and the internal pressure is released from within the case.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: March 10, 2020
    Assignee: NICHICON CORPORATION
    Inventors: Mitsuru Yoneda, Takaya Sakai, Kenta Kawanishi, Kazuya Yamanaka
  • Patent number: 10529735
    Abstract: A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: January 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Reiko Komiya, Tatsuo Izumi, Takaya Yamanaka, Takeshi Nagatomo, Karin Takagi
  • Patent number: 10475806
    Abstract: A semiconductor memory device includes a substrate with a first insulating film thereon, a wiring in the first insulating film, a first electrode film on the first insulating film, a stacked body on the first electrode film, made of alternating second insulating films and second electrode films, a first insulating member extending in a direction to penetrate the stacked body, a first semiconductor film around the first insulating member and connected to the first electrode film, a third insulating film around the first semiconductor film, a first conductive member extending in the direction to penetrate the stacked body and the first electrode film, and connected to the wiring, and a fourth insulating film around the first conductive member. The fourth insulating film has the same film structure as the third insulating film.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: November 12, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mikiko Yagi, Hideto Takekida, Takaya Yamanaka, Masaharu Mizutani, Hideo Wada
  • Publication number: 20190287997
    Abstract: A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.
    Type: Application
    Filed: September 11, 2018
    Publication date: September 19, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Reiko Komiya, Tatsuo Izumi, Takaya Yamanaka, Takeshi Nagatomo, Karin Takagi
  • Publication number: 20190198523
    Abstract: A semiconductor memory device includes first and second wiring layers above a semiconductor substrate, a memory pillar extending through the first and second wiring layers, a first plug contacting the first wiring layer, a second plug contacting the second wiring layer, a first pillar adjacent to the first plug and extending through the first wiring layer, and a second pillar adjacent to the second plug and extending through the first and second wiring layers. The memory pillar includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer on a side surface of the second semiconductor layer. The distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar.
    Type: Application
    Filed: September 3, 2018
    Publication date: June 27, 2019
    Inventors: Yusuke NAKANISHI, Takaya YAMANAKA, Akira MATSUMURA
  • Patent number: 10276590
    Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: April 30, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsufumi Hamada, Hikari Tajima, Takashi Izumida, Nobutoshi Aoki, Shinya Naito, Takayuki Kakegawa, Takaya Yamanaka
  • Publication number: 20190081063
    Abstract: A memory device includes a conductive layer, a first electrode over the conductive layer, and a second electrode between the conductive layer and the first electrode. The second electrode is a material different from that of the first electrode. A semiconductor pillar extends through the first and second electrodes, and has an end connected to the conductive layer. A first insulating film is between the semiconductor pillar and the first and second electrodes and between at least a portion of the semiconductor pillar and the conductive layer. A second insulating film is between the conductive layer and the first insulating film. A third insulating film is between the first insulating film and the second electrode, and between the second and third insulating film. The second electrode and conductive layer include a first element and the second and third insulating films comprise an oxide or nitride of the first element.
    Type: Application
    Filed: March 1, 2018
    Publication date: March 14, 2019
    Inventor: Takaya YAMANAKA
  • Publication number: 20190074287
    Abstract: A semiconductor memory device includes a substrate with a first insulating film thereon, a wiring in the first insulating film, a first electrode film on the first insulating film, a stacked body on the first electrode film, made of alternating second insulating films and second electrode films, a first insulating member extending in a direction to penetrate the stacked body, a first semiconductor film around the first insulating member and connected to the first electrode film, a third insulating film around the first semiconductor film, a first conductive member extending in the direction to penetrate the stacked body and the first electrode film, and connected to the wiring, and a fourth insulating film around the first conductive member. The fourth insulating film has the same film structure as the third insulating film.
    Type: Application
    Filed: February 28, 2018
    Publication date: March 7, 2019
    Inventors: Mikiko YAGI, Hideto Takekida, Takaya Yamanaka, Masaharu Mizutani, Hideo Wada
  • Patent number: 10224240
    Abstract: A first tier structure is provided by forming first memory openings through a first alternating stack of first insulating layers and first spacer layers, and by forming sacrificial memory opening fill structures in the first memory openings. A second tier structure is formed over the first tier structure by forming a second alternating stack of second insulating layers and second spacer layers. Second memory openings are formed through the second tier structure in areas of the sacrificial memory opening fill structures. Distortion of the first tier structure and misalignment between the first and second memory openings is reduced or prevented by conducting thermal cycles at a lower temperature for the second tier structure than for the first tier structure.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: March 5, 2019
    Assignees: SANDISK TECHNOLOGIES LLC, TOSHIBA MEMORY CORPORATION
    Inventors: Kota Funayama, Masayuki Fukai, Takaya Yamanaka, Masaki Tsuji, Akira Matsumura
  • Patent number: 10211222
    Abstract: A memory device includes a conductive layer, a first electrode over the conductive layer, and a second electrode between the conductive layer and the first electrode. The second electrode is a material different from that of the first electrode. A semiconductor pillar extends through the first and second electrodes, and has an end connected to the conductive layer. A first insulating film is between the semiconductor pillar and the first and second electrodes and between at least a portion of the semiconductor pillar and the conductive layer. A second insulating film is between the conductive layer and the first insulating film. A third insulating film is between the first insulating film and the second electrode, and between the second and third insulating film. The second electrode and conductive layer include a first element and the second and third insulating films comprise an oxide or nitride of the first element.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: February 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Takaya Yamanaka
  • Publication number: 20180175056
    Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.
    Type: Application
    Filed: February 14, 2018
    Publication date: June 21, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsufumi HAMADA, Hikari TAJIMA, Takashi IZUMIDA, Nobutoshi AOKI, Shinya NAITO, Takayuki KAKEGAWA, Takaya YAMANAKA
  • Patent number: 9917099
    Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: March 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsufumi Hamada, Hikari Tajima, Takashi Izumida, Nobutoshi Aoki, Shinya Naito, Takayuki Kakegawa, Takaya Yamanaka
  • Publication number: 20170263635
    Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.
    Type: Application
    Filed: September 14, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsufumi HAMADA, Hikari TAJIMA, Takashi IZUMIDA, Nobutoshi AOKI, Shinya NAITO, Takayuki KAKEGAWA, Takaya YAMANAKA
  • Publication number: 20160372601
    Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a tunnel insulating film disposed on a semiconductor layer; a floating gate electrode disposed on the tunnel insulating film; a block insulating film disposed on the floating gate electrode; and a control gate electrode disposed on the block insulating film. The block insulating film is provided along a bottom surface and a side surface of the control gate electrode.
    Type: Application
    Filed: November 2, 2015
    Publication date: December 22, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takaya YAMANAKA, Hiroto Sugiura
  • Publication number: 20150262896
    Abstract: An evaluation element includes a plurality of first wirings extending in a first direction, connection conductors, each connection conductor electrically contact a single one of the first wirings, and a plurality of second wirings extending in a second direction that crosses the first direction and electrically contacts the connection conductors contacting the first wirings. The connection conductors are provided in at least two separated positions on the same first wiring. The plurality of second wiring are positioned such that a series electrical connection is established, through the connection conductors and the first wirings, between one second wiring and another second wiring.
    Type: Application
    Filed: December 4, 2014
    Publication date: September 17, 2015
    Inventors: Takaya YAMANAKA, Akira YOTSUMOTO
  • Patent number: 8981522
    Abstract: A nonvolatile semiconductor storage device includes a substrate; an isolation film extending in a first direction and dividing the substrate into element regions; a cell string including memory cells in the element regions; a cell unit including the cell string and a select transistor on first directional ends of the cell string; diffusion layers formed in a portion of the element region first directionally beside the select gate electrode, the diffusion layers being adjacent to one another in a second direction intersecting with the first direction; and contacts extending through an interlayer insulating film and contacting the diffusion layers. An upper surface of the isolation film located between the diffusion layers is lower than an upper surface of the substrate. A laminate of silicon oxide film and a silicon nitride film are located above the upper surface of the isolation film and below the upper surface of the substrate.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Fujii, Akira Yotsumoto, Takaya Yamanaka, Fumie Kikushima
  • Patent number: 8885396
    Abstract: According to one embodiment, a memory device includes: a first signal line; a second signal line; a transistor; a memory region; and a conductive region. The transistor controls a conduction of each of a current in a first direction flowing between the first line and the second line and a current in a second direction opposite to the first direction. The memory region has a first magnetic tunnel junction element which is connected between the first line and one end of the transistor, a magnetization direction of which becomes parallel when a current not less than a first parallel threshold value flows in the first direction, and the magnetization direction of which becomes antiparallel when a current not less than a first antiparallel threshold value flows in the second direction. The conductive region is connected between the second line and the other end of the transistor.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: November 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takaya Yamanaka, Susumu Shuto