Patents by Inventor Takaya Yamanaka
Takaya Yamanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210249440Abstract: A memory device includes a conductive layer, a plurality of first electrode layers, a first semiconductor layer extending through the plurality of first electrode layers in a first direction toward the plurality of first electrode layers from the conductive layer, a first insulating film including a tunneling insulator film, a charge-trapping film and a blocking insulator film, a second electrode layer, and a semiconductor base. The charge-trapping film is spaced along the first direction from the semiconductor base, a distance in the first direction between the charge-trapping film and the semiconductor base is larger than a thickness of the blocking insulator film in a second direction toward the plurality of first electrode layers from the first semiconductor layer.Type: ApplicationFiled: April 28, 2021Publication date: August 12, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Reiko KOMIYA, Tatsuo IZUMI, Takaya YAMANAKA, Takeshi NAGATOMO, Karin TAKAGI
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Patent number: 11024646Abstract: A memory device includes a conductive layer, a plurality of first electrode layers, a first semiconductor layer extending through the plurality of first electrode layers in a first direction toward the plurality of first electrode layers from the conductive layer, a first insulating film including a tunneling insulator film, a charge-trapping film and a blocking insulator film, a second electrode layer, and a semiconductor base. The charge-trapping film is spaced along the first direction from the semiconductor base, a distance in the first direction between the charge-trapping film and the semiconductor base is larger than a thickness of the blocking insulator film in a second direction toward the plurality of first electrode layers from the first semiconductor layer.Type: GrantFiled: November 26, 2019Date of Patent: June 1, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Reiko Komiya, Tatsuo Izumi, Takaya Yamanaka, Takeshi Nagatomo, Karin Takagi
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Publication number: 20210082954Abstract: A semiconductor memory device includes first and second wiring layers above a semiconductor substrate, a memory pillar extending through the first and second wiring layers, a first plug contacting the first wiring layer, a second plug contacting the second wiring layer, a first pillar adjacent to the first plug and extending through the first wiring layer, and a second pillar adjacent to the second plug and extending through the first and second wiring layers. The memory pillar includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer on a side surface of the second semiconductor layer. The distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Inventors: Yusuke NAKANISHI, Takaya YAMANAKA, Akira MATSUMURA
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Publication number: 20200212066Abstract: A semiconductor memory device includes first and second wiring layers above a semiconductor substrate, a memory pillar extending through the first and second wiring layers, a first plug contacting the first wiring layer, a second plug contacting the second wiring layer, a first pillar adjacent to the first plug and extending through the first wiring layer, and a second pillar adjacent to the second plug and extending through the first and second wiring layers. The memory pillar includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer on a side surface of the second semiconductor layer. The distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar.Type: ApplicationFiled: March 9, 2020Publication date: July 2, 2020Inventors: Yusuke NAKANISHI, Takaya YAMANAKA, Akira MATSUMURA
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Publication number: 20200098790Abstract: A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.Type: ApplicationFiled: November 26, 2019Publication date: March 26, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Reiko KOMIYA, Tatsuo IZUMI, Takaya YAMANAKA, Takeshi NAGATOMO, Karin TAKAGI
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Patent number: 10600803Abstract: A semiconductor memory device includes first and second wiring layers above a semiconductor substrate, a memory pillar extending through the first and second wiring layers, a first plug contacting the first wiring layer, a second plug contacting the second wiring layer, a first pillar adjacent to the first plug and extending through the first wiring layer, and a second pillar adjacent to the second plug and extending through the first and second wiring layers. The memory pillar includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer on a side surface of the second semiconductor layer. The distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar.Type: GrantFiled: September 3, 2018Date of Patent: March 24, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yusuke Nakanishi, Takaya Yamanaka, Akira Matsumura
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Patent number: 10529735Abstract: A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.Type: GrantFiled: September 11, 2018Date of Patent: January 7, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Reiko Komiya, Tatsuo Izumi, Takaya Yamanaka, Takeshi Nagatomo, Karin Takagi
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Patent number: 10475806Abstract: A semiconductor memory device includes a substrate with a first insulating film thereon, a wiring in the first insulating film, a first electrode film on the first insulating film, a stacked body on the first electrode film, made of alternating second insulating films and second electrode films, a first insulating member extending in a direction to penetrate the stacked body, a first semiconductor film around the first insulating member and connected to the first electrode film, a third insulating film around the first semiconductor film, a first conductive member extending in the direction to penetrate the stacked body and the first electrode film, and connected to the wiring, and a fourth insulating film around the first conductive member. The fourth insulating film has the same film structure as the third insulating film.Type: GrantFiled: February 28, 2018Date of Patent: November 12, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Mikiko Yagi, Hideto Takekida, Takaya Yamanaka, Masaharu Mizutani, Hideo Wada
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Publication number: 20190287997Abstract: A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.Type: ApplicationFiled: September 11, 2018Publication date: September 19, 2019Applicant: Toshiba Memory CorporationInventors: Reiko Komiya, Tatsuo Izumi, Takaya Yamanaka, Takeshi Nagatomo, Karin Takagi
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Publication number: 20190198523Abstract: A semiconductor memory device includes first and second wiring layers above a semiconductor substrate, a memory pillar extending through the first and second wiring layers, a first plug contacting the first wiring layer, a second plug contacting the second wiring layer, a first pillar adjacent to the first plug and extending through the first wiring layer, and a second pillar adjacent to the second plug and extending through the first and second wiring layers. The memory pillar includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer on a side surface of the second semiconductor layer. The distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar.Type: ApplicationFiled: September 3, 2018Publication date: June 27, 2019Inventors: Yusuke NAKANISHI, Takaya YAMANAKA, Akira MATSUMURA
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Patent number: 10276590Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.Type: GrantFiled: February 14, 2018Date of Patent: April 30, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tatsufumi Hamada, Hikari Tajima, Takashi Izumida, Nobutoshi Aoki, Shinya Naito, Takayuki Kakegawa, Takaya Yamanaka
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Publication number: 20190081063Abstract: A memory device includes a conductive layer, a first electrode over the conductive layer, and a second electrode between the conductive layer and the first electrode. The second electrode is a material different from that of the first electrode. A semiconductor pillar extends through the first and second electrodes, and has an end connected to the conductive layer. A first insulating film is between the semiconductor pillar and the first and second electrodes and between at least a portion of the semiconductor pillar and the conductive layer. A second insulating film is between the conductive layer and the first insulating film. A third insulating film is between the first insulating film and the second electrode, and between the second and third insulating film. The second electrode and conductive layer include a first element and the second and third insulating films comprise an oxide or nitride of the first element.Type: ApplicationFiled: March 1, 2018Publication date: March 14, 2019Inventor: Takaya YAMANAKA
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Publication number: 20190074287Abstract: A semiconductor memory device includes a substrate with a first insulating film thereon, a wiring in the first insulating film, a first electrode film on the first insulating film, a stacked body on the first electrode film, made of alternating second insulating films and second electrode films, a first insulating member extending in a direction to penetrate the stacked body, a first semiconductor film around the first insulating member and connected to the first electrode film, a third insulating film around the first semiconductor film, a first conductive member extending in the direction to penetrate the stacked body and the first electrode film, and connected to the wiring, and a fourth insulating film around the first conductive member. The fourth insulating film has the same film structure as the third insulating film.Type: ApplicationFiled: February 28, 2018Publication date: March 7, 2019Inventors: Mikiko YAGI, Hideto Takekida, Takaya Yamanaka, Masaharu Mizutani, Hideo Wada
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Patent number: 10224240Abstract: A first tier structure is provided by forming first memory openings through a first alternating stack of first insulating layers and first spacer layers, and by forming sacrificial memory opening fill structures in the first memory openings. A second tier structure is formed over the first tier structure by forming a second alternating stack of second insulating layers and second spacer layers. Second memory openings are formed through the second tier structure in areas of the sacrificial memory opening fill structures. Distortion of the first tier structure and misalignment between the first and second memory openings is reduced or prevented by conducting thermal cycles at a lower temperature for the second tier structure than for the first tier structure.Type: GrantFiled: June 27, 2017Date of Patent: March 5, 2019Assignees: SANDISK TECHNOLOGIES LLC, TOSHIBA MEMORY CORPORATIONInventors: Kota Funayama, Masayuki Fukai, Takaya Yamanaka, Masaki Tsuji, Akira Matsumura
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Patent number: 10211222Abstract: A memory device includes a conductive layer, a first electrode over the conductive layer, and a second electrode between the conductive layer and the first electrode. The second electrode is a material different from that of the first electrode. A semiconductor pillar extends through the first and second electrodes, and has an end connected to the conductive layer. A first insulating film is between the semiconductor pillar and the first and second electrodes and between at least a portion of the semiconductor pillar and the conductive layer. A second insulating film is between the conductive layer and the first insulating film. A third insulating film is between the first insulating film and the second electrode, and between the second and third insulating film. The second electrode and conductive layer include a first element and the second and third insulating films comprise an oxide or nitride of the first element.Type: GrantFiled: March 1, 2018Date of Patent: February 19, 2019Assignee: Toshiba Memory CorporationInventor: Takaya Yamanaka
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Publication number: 20180175056Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.Type: ApplicationFiled: February 14, 2018Publication date: June 21, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tatsufumi HAMADA, Hikari TAJIMA, Takashi IZUMIDA, Nobutoshi AOKI, Shinya NAITO, Takayuki KAKEGAWA, Takaya YAMANAKA
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Patent number: 9917099Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.Type: GrantFiled: September 14, 2016Date of Patent: March 13, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tatsufumi Hamada, Hikari Tajima, Takashi Izumida, Nobutoshi Aoki, Shinya Naito, Takayuki Kakegawa, Takaya Yamanaka
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Publication number: 20170263635Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.Type: ApplicationFiled: September 14, 2016Publication date: September 14, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Tatsufumi HAMADA, Hikari TAJIMA, Takashi IZUMIDA, Nobutoshi AOKI, Shinya NAITO, Takayuki KAKEGAWA, Takaya YAMANAKA
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Publication number: 20160372601Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a tunnel insulating film disposed on a semiconductor layer; a floating gate electrode disposed on the tunnel insulating film; a block insulating film disposed on the floating gate electrode; and a control gate electrode disposed on the block insulating film. The block insulating film is provided along a bottom surface and a side surface of the control gate electrode.Type: ApplicationFiled: November 2, 2015Publication date: December 22, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Takaya YAMANAKA, Hiroto Sugiura
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Publication number: 20150262896Abstract: An evaluation element includes a plurality of first wirings extending in a first direction, connection conductors, each connection conductor electrically contact a single one of the first wirings, and a plurality of second wirings extending in a second direction that crosses the first direction and electrically contacts the connection conductors contacting the first wirings. The connection conductors are provided in at least two separated positions on the same first wiring. The plurality of second wiring are positioned such that a series electrical connection is established, through the connection conductors and the first wirings, between one second wiring and another second wiring.Type: ApplicationFiled: December 4, 2014Publication date: September 17, 2015Inventors: Takaya YAMANAKA, Akira YOTSUMOTO