Patents by Inventor Takayoshi Shimura

Takayoshi Shimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190355828
    Abstract: A semiconductor device has an MIS structure that includes a semiconductor layer, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. The gate insulating film has a layered structure that includes a base SiO2 layer and a high-k layer on the base SiO2 layer and containing Hf. The gate electrode has a portion made of a metal material having a work function of higher than 4.6 eV, the portion being in contact with at least the high-k layer.
    Type: Application
    Filed: July 13, 2017
    Publication date: November 21, 2019
    Applicant: ROHM CO., LTD.
    Inventors: Kenji YAMAMOTO, Masatoshi AKETA, Hirokazu ASAHARA, Takashi NAKAMURA, Takuji HOSOI, Heiji WATANABE, Takayoshi SHIMURA, Shuji AZUMO, Yusaku KASHIWAGI
  • Publication number: 20190343472
    Abstract: An X-ray phase contrast imaging device of the present invention can change an arrangement pitch of slits related to a multi-slit and an arrangement pitch of phase shift sections related to a phase grating. A positional relationship among the multi-slit 3b, the phase grating, and an FPD is determined based on the arrangement pitch of the slits related to the multi-slit, the arrangement pitch of the phase shift sections related to the phase grating, and an arrangement pitch of detection elements related to the FPD. Among these arrangement pitches, by changing the arrangement pitch of the slits and the arrangement pitch of the phase shift sections, the present invention can change the positional relationship among the multi-slit, the phase grating, and the FPD.
    Type: Application
    Filed: July 28, 2017
    Publication date: November 14, 2019
    Inventors: Satoshi SANO, Koichi TANABE, Toshinori YOSHIMUTA, Kenji KIMURA, Hiroyuki KISHIHARA, Yukihisa WADA, Takuro IZUMI, Taro SHIRAI, Takahiro DOKI, Akira HORIBA, Takayoshi SHIMURA, Heiji WATANABE, Takuji HOSOI
  • Publication number: 20190273158
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.
    Type: Application
    Filed: May 21, 2019
    Publication date: September 5, 2019
    Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
  • Patent number: 10319853
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 11, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
  • Publication number: 20190167219
    Abstract: This X-ray phase contrast imaging apparatus (100) includes an X-ray source (1) that radiates continuous X-rays, a first grating (3) that forms a self-image, a second grating (4), a detector (5) that detects the continuous X-rays, and a third grating (2) arranged between the detector (5) and the first grating 3. The first grating (3), the second grating (4), and the third grating (2) are arranged so as to satisfy conditions of predetermined formulas.
    Type: Application
    Filed: July 10, 2017
    Publication date: June 6, 2019
    Inventors: Satoshi SANO, Koichi TANABE, Toshinori YOSHIMUTA, Kenji KIMURA, Hiroyuki KISHIHARA, Yukihisa WADA, Takuro IZUMI, Taro SHIRAI, Takahiro DOKI, Akira HORIBA, Takayoshi SHIMURA, Heiji WATANABE, Takuji HOSOI
  • Publication number: 20190056336
    Abstract: [PROBLEM TO BE SOLVED] To provide a radiation phase contrast imaging device having a small device configuration [SOLVING MEANS] The present invention focused on the findings that the distance between the phase grating 5 and the FPD 4 does not need to be the Talbot distance. The distance between the phase grating 5 and the FPD 4 can be more freely set. However, a self-image cannot be detected unless the self-image is sufficiently magnified with respect to the phase grating 5. The degree on how much the self-image is magnified on the FPD 4 with respect to the original phase grating 5 is determined by a magnification ratio X2/X1. Therefore, in the present invention, the magnification ratio is set to be the same as the magnification ratio in a conventional configuration. With this, even if the distance X2 between the radiation source 3 and the FPD 4 is reduced, a situation in which the self-image cannot be detected by the FPD 4 due to the excessively small size thereof does not occur.
    Type: Application
    Filed: February 22, 2017
    Publication date: February 21, 2019
    Applicants: SHIMADZU CORPORATION, OSAKA UNIVERSITY
    Inventors: Takahiro DOKI, Koichi TANABE, Toshinori YOSHIMUTA, Kenji KIMURA, Akihiro NISHIMURA, Taro SHIRAI, Satoshi SANO, Akira HORIBA, Takayoshi SHIMURA, Heiji WATANABE, Takuji HOSOI
  • Patent number: 10103232
    Abstract: A semiconductor device (100) includes a base layer (10), an interface layer (20), and a deposition layer (30). The base layer (10) includes a nitride semiconductor that contains gallium. The interface layer (20) is adjacent to the base layer (10). The interface layer (20) contains gallium oxide. The deposition layer (30) is adjacent to the interface layer (20). The deposition layer (30) has a wider band gap than the interface layer (20). The interface layer (20) preferably has crystallinity. The interface layer (20) preferably contains ?-phase Ga2O3.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 16, 2018
    Assignee: OSAKA UNIVERSITY
    Inventors: Heiji Watanabe, Takahiro Yamada, Mikito Nozaki, Takuji Hosoi, Takayoshi Shimura
  • Publication number: 20180138313
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.
    Type: Application
    Filed: January 11, 2018
    Publication date: May 17, 2018
    Applicant: ROHM CO., LTD.
    Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
  • Publication number: 20180061954
    Abstract: A semiconductor device (100) includes a base layer (10), an interface layer (20), and a deposition layer (30). The base layer (10) includes a nitride semiconductor that contains gallium. The interface layer (20) is adjacent to the base layer (10). The interface layer (20) contains gallium oxide. The deposition layer (30) is adjacent to the interface layer (20). The deposition layer (30) has a wider band gap than the interface layer (20). The interface layer (20) preferably has crystallinity. The interface layer (20) preferably contains ?-phase Ga2O3.
    Type: Application
    Filed: August 25, 2017
    Publication date: March 1, 2018
    Applicant: OSAKA UNIVERSITY
    Inventors: Heiji WATANABE, Takahiro YAMADA, Mikito NOZAKI, Takuji HOSOI, Takayoshi SHIMURA
  • Patent number: 9893180
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: February 13, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
  • Patent number: 9805944
    Abstract: A p-type base region, n+-type source region, p+-type contact region, and n-type JFET region are formed on a front surface side of a silicon carbide base by ion implantation. The front surface of the silicon carbide base is thermally oxidized, forming a thermal oxide film. Activation annealing at a high temperature of 1500 degrees C. or higher is performed with the front surface of the silicon carbide base being covered by the thermal oxide film. The activation annealing is performed in a gas atmosphere that includes oxygen at a partial pressure from 0.01 atm to 1 atm and therefore, the thermal oxide film thickness may be maintained or increased without a decrease thereof. The thermal oxide film is used as a gate insulating film and thereafter, a poly-silicon layer that is to become a gate electrode is deposited on the thermal oxide film, forming a MOS gate structure.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: October 31, 2017
    Assignees: OSAKA UNIVERSITY, FUJI ELECTRIC CO., LTD.
    Inventors: Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Mitsuru Sometani
  • Publication number: 20170271168
    Abstract: A p-type base region, n+-type source region, p+-type contact region, and n-type JFET region are formed on a front surface side of a silicon carbide base by ion implantation. The front surface of the silicon carbide base is thermally oxidized, forming a thermal oxide film. Activation annealing at a high temperature of 1500 degrees C. or higher is performed with the front surface of the silicon carbide base being covered by the thermal oxide film. The activation annealing is performed in a gas atmosphere that includes oxygen at a partial pressure from 0.01 atm to 1 atm and therefore, the thermal oxide film thickness may be maintained or increased without a decrease thereof. The thermal oxide film is used as a gate insulating film and thereafter, a poly-silicon layer that is to become a gate electrode is deposited on the thermal oxide film, forming a MOS gate structure.
    Type: Application
    Filed: February 28, 2017
    Publication date: September 21, 2017
    Applicants: OSAKA UNIVERSITY, FUJI ELECTRIC CO., LTD.
    Inventors: Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Mitsuru SOMETANI
  • Publication number: 20170069487
    Abstract: A method for manufacturing a semiconductor device includes: thermally-oxidizing a surface of a to-be-processed base made by SiC as body material to form a silicon dioxide film, by supplying gas containing oxidation agent to the surface of the to-be-processed base; exchanging ambient gas containing the oxidation agent after forming the silicon dioxide film, by decreasing a partial pressure of the oxidation agent in the ambient gas to 10 Pa or less; and after exchanging the ambient gas, lowering a temperature of the to-be-processed base.
    Type: Application
    Filed: July 27, 2016
    Publication date: March 9, 2017
    Applicants: OSAKA UNIVERSITY, FUJI ELECTRIC CO., LTD.
    Inventors: Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Mitsuru SOMETANI
  • Publication number: 20170012123
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.
    Type: Application
    Filed: September 22, 2016
    Publication date: January 12, 2017
    Applicant: ROHM CO., LTD.
    Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
  • Patent number: 9496393
    Abstract: A semiconductor device includes a semiconductor layer made of first conductivity type semiconductor layer; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: November 15, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
  • Patent number: 9397185
    Abstract: A semiconductor device according to the present invention has a MIS structure that includes a semiconductor layer, a gate insulating film in contact with the semiconductor layer, and a gate electrode formed on the gate insulating film, and the gate insulating film includes an AlON layer with a nitrogen composition of 5% to 40%. A semiconductor device is thereby provided with which electron trapping in the gate insulating film can be reduced and shifting of a threshold voltage Vth can be suppressed.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: July 19, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Heiji Watanabe, Takuji Hosoi, Takayoshi Shimura, Ryota Nakamura, Yuki Nakano, Shuhei Mitani, Takashi Nakamura, Hirokazu Asahara
  • Patent number: 9368351
    Abstract: [Problem] To provide an SiC semiconductor device, with which stabilization of high-temperature operation can be achieved by decreasing mobile ions in a gate insulating film, and a method for manufacturing the SiC semiconductor device. [Solution Means] A semiconductor device 1 has an MIS structure including an SiC epitaxial layer 3, a gate insulating film 9 and a gate electrode 10 formed on the gate insulating film 9. A gate insulating film 9 includes a silicon oxide film in contact with the SiC epitaxial layer 3. In the MIS structure, an area density QM of positive mobile ions in the gate insulating film 9 is made no more than 1×1012 cm?2.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: June 14, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Shuhei Mitani, Yuki Nakano, Ryota Nakamura, Takashi Nakamura
  • Publication number: 20160133743
    Abstract: A semiconductor device includes a semiconductor layer made of first conductivity type semiconductor layer; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.
    Type: Application
    Filed: January 14, 2016
    Publication date: May 12, 2016
    Applicant: ROHM CO., LTD.
    Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
  • Patent number: 9293543
    Abstract: Provided is a method of forming a gate insulating film for use in a MOSFET for a power device. An AlN film is formed on a SiC substrate of a wafer W and then the formation of an AlO film and the formation of an AlN film on the formed AlO film are repeated, thereby forming an AlON film having a laminated structure in which AlO films and AlN films are alternately laminated. A heat treatment is performed on the AlON film having the laminated structure.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: March 22, 2016
    Assignees: TOKYO ELECTRON LIMITED, OSAKA UNIVERSITY
    Inventors: Shuji Azumo, Yusaku Kashiwagi, Yuichiro Morozumi, Yu Wamura, Katsushige Harada, Kosuke Takahashi, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi
  • Patent number: 9257521
    Abstract: A semiconductor device includes a semiconductor layer made of first conductivity type SiC; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: February 9, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino