Abstract: An apparatus comprising a memory array comprising wordlines, digit lines, and memory cells, with each memory cell coupled to an associated wordline and an associated digit line. Each memory cell comprises a monocrystalline silicon material adjacent to an access device, a monocrystalline metal silicide material directly contacting the monocrystalline semiconductor material, a metal material directly contacting the monocrystalline metal silicide material, and a storage device adjacent to the metal material. Electronic devices, electronic systems, and methods of forming an electronic device are also disclosed.

Abstract: An apparatus comprising a memory array comprising wordlines, digit lines, and memory cells, with each memory cell coupled to an associated wordline and an associated digit line. Each memory cell comprises a monocrystalline silicon material adjacent to an access device, a monocrystalline metal silicide material directly contacting the monocrystalline semiconductor material, a metal material directly contacting the monocrystalline metal silicide material, and a storage device adjacent to the metal material. Electronic devices, electronic systems, and methods of forming an electronic device are also disclosed.

Abstract: A semiconductor device comprises an array region, a dummy region, pillars of an electrically insulative material in the array region and the dummy region. The semiconductor device further comprises electrically conductive contacts between adjacent pillars of the electrically insulative material in the array region, another electrically insulative material between adjacent pillars of the electrically insulative material in the dummy region, an electrically conductive material over the conductive contacts in the array region and over the electrically insulative material in the dummy region, and an oxide between the electrically conductive material in the dummy region and the electrically insulative material in the dummy region. Related semiconductor devices, systems, and methods are also disclosed.

Abstract: An integrated circuitry construction comprises a first area and a second area aside the first area. Laterally-alternating first and second conductive lines extend from the first area into the second area. The second conductive lines extend laterally deeper into the second area on one side of the first area than the first conductive lines and comprise pairs of immediately-laterally-adjacent of the second conductive lines. Insulative material is in the second area laterally between the immediately-laterally-adjacent second conductive lines in individual of the pairs. An elevationally-extending wall of insulator material is within the insulative material in the second area. The wall extends laterally between immediately-laterally-adjacent of the second conductive lines within the respective individual pair and laterally all across the first conductive line that is laterally between the immediately-laterally-adjacent second conductive lines within the respective individual pair.

Abstract: A method of forming a plurality of conductive vias comprises forming spaced contact openings individually having two opposing sidewalls comprising SiwBxOyNz, where “w” is from 0.1 to 0.3, “x” is from 0.1 to 0.4, “y” is from 0 to 0.2, and “z” is from 0.4 to 0.6. A lining comprising silicon nitride is formed over the two opposing sidewalls in individual of the contact openings. A conductive via is formed in the individual contact openings over the lining. Integrated circuitry is disclosed.

Abstract: A method of forming a plurality of conductive vias comprises forming spaced contact openings individually having two opposing sidewalls comprising SiwBxOyNz, where “w” is from 0.1 to 0.3, “x” is from 0.1 to 0.4, “y” is from 0 to 0.2, and “z” is from 0.4 to 0.6. A lining comprising silicon nitride is formed over the two opposing sidewalls in individual of the contact openings. A conductive via is formed in the individual contact openings over the lining. Integrated circuitry is disclosed.

Abstract: An integrated circuitry construction comprises a first area and a second area aside the first area. Laterally-alternating first and second conductive lines extend from the first area into the second area. The second conductive lines extend laterally deeper into the second area on one side of the first area than the first conductive lines and comprise pairs of immediately-laterally-adjacent of the second conductive lines. Insulative material is in the second area laterally between the immediately-laterally-adjacent second conductive lines in individual of the pairs. An elevationally-extending wall of insulator material is within the insulative material in the second area. The wall extends laterally between immediately-laterally-adjacent of the second conductive lines within the respective individual pair and laterally all across the first conductive line that is laterally between the immediately-laterally-adjacent second conductive lines within the respective individual pair.

Abstract: A semiconductor device comprises an array region, a dummy region, pillars of an electrically insulative material in the array region and the dummy region. The semiconductor device further comprises electrically conductive contacts between adjacent pillars of the electrically insulative material in the array region, another electrically insulative material between adjacent pillars of the electrically insulative material in the dummy region, an electrically conductive material over the conductive contacts in the array region and over the electrically insulative material in the dummy region, and an oxide between the electrically conductive material in the dummy region and the electrically insulative material in the dummy region. Related semiconductor devices, systems, and methods are also disclosed.

Abstract: A method for diagnosing a risk for preterm delivery or miscarriage in a pregnant woman and preventing preterm delivery or miscarriage in the pregnant woman who has been determined to have the risk is provided. The method includes measuring plasminogen activator inhibitor-1 activity or level in plasma isolated from a pregnant woman. The method also includes determining that the pregnant woman has a risk for preterm delivery or miscarriage when the activity or the level is lower than that in the plasma of a normal pregnant woman. The method also includes administering plasminogen activator inhibitor-1 to the pregnant woman who has been determined to have the risk. A kit for the diagnosis of the degree of risk for preterm delivery or miscarriage also is provided. A pharmaceutical composition for the prevention of preterm delivery or miscarriage, comprising plasminogen activator inhibitor-1, also is provided.

Abstract: A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.

Abstract: The present invention relates to a method for diagnosing the degree of risk for preterm delivery or miscarriage, comprising measuring plasminogen activator inhibitor activity or level in plasma. Specifically, the present invention relates to: a method for diagnosing the degree of risk for preterm delivery or miscarriage, wherein when the plasminogen activator inhibitor activity or level is lower than those of normal pregnant woman, the degree of risk for preterm delivery or miscarriage is determined to be high; a kit for the diagnosis of the degree of risk for preterm delivery or miscarriage; and a pharmaceutical composition for the prevention of preterm delivery or miscarriage, comprising plasminogen activator inhibitor-1.

Abstract: A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.

Abstract: A semiconductor device includes a lower wiring layer including a plurality of lower wirings, each of the lower wirings being elongated to run substantially parallel to a first direction, a metal-insulator-metal (MIM) capacitor formed above the plurality of lower wirings, the MIM capacitor comprising lower and upper electrodes and a capacity dielectric film interposed between the lower and upper electrodes, and an upper wiring layer formed above the MIM capacitor, the upper wiring layer including a plurality of upper wirings which are connected to the lower and upper electrodes through a plurality of first via plus and a plurality of second via plugs, respectively. Each of the plurality of first via plugs and the plurality of second via plugs are arranged parallel to the first direction, and the plurality of second via plus is arranged above portions between the lower wirings.

Abstract: A semiconductor device includes a lower layer wiring layer, an MIM capacitors and an upper layer wiring layer. The lower layer wiring layer includes a plurality of lower layer wirings. The MIM capacitor is formed above the lower layer wiring layer. The MIM capacitor includes a lower electrode, a capacity dielectric film and an upper electrode which are layered from underneath in this order. A planar form of the upper electrode is smaller than that of the lower electrode. The upper layer wiring layer includes a plurality of upper layer wirings which are connected to the lower electrode and the upper electrode through via plugs. A plane of the upper electrode is made rectangular. The lower layer wirings are not arranged right below one or more than one edge of the plane of the upper electrode.

Abstract: Provided is a semiconductor device including a MIM capacitor, and having excellent waterproof property and antioxidant property even when being formed between wiring layers. The semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first wiring layer embedded in the first insulating film, a wiring cap film for covering the first wiring layer, the MIM capacitor formed on the wiring cap film, a hydrogen barrier film for covering the MIM capacitor, a second insulating film formed on the hydrogen barrier film, conductive plugs passing through the second insulating film and the hydrogen barrier film, one of which being connected to an upper electrode of the MIM capacitor and the other of which being connected to a lower electrode of the MIM capacitor, and a second wiring layer connected to the conductive plugs, and the upper and lower electrodes of the MIM capacitor.

Abstract: A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.

Abstract: In order to solve a problem of occurrence of delamination of interlayer film due to occurrence of a crack in an LSI wiring layer in a UBM lower layer immediately under a solder bump in an outer periphery of an LSI chip, a semiconductor apparatus of the present invention includes a stress boundary between compressive stress and tensile stress in an LSI wiring layer of a bump lower layer and in order to alleviate the stress present in the bump lower layer tensile stress material is arranged on a compressive stress side or compressive stress material is arranged on a tensile stress side with a stress boundary of the LSI wiring layer as a boundary.

Abstract: A semiconductor device includes a lower layer wiring layer, an MIM capacitors and an upper layer wiring layer. The lower layer wiring layer includes a plurality of lower layer wirings. The MIM capacitor is formed above the lower layer wiring layer. The MIM capacitor includes a lower electrode, a capacity dielectric film and an upper electrode which are layered from underneath in this order. A planar form of the upper electrode is smaller than that of the lower electrode. The upper layer wiring layer includes a plurality of upper layer wirings which are connected to the lower electrode and the upper electrode through via plugs. A plane of the upper electrode is made rectangular. The lower layer wirings are not arranged right below one or more than one edge of the plane of the upper electrode.

Abstract: Provided is a semiconductor device including: an MIM capacitor that includes a lower electrode, an upper electrode, and a capacitor insulating film formed between the lower electrode and the upper electrode; a first via hole that connects to the lower electrode and extends in a normal upward direction of a principal surface of the lower electrode; a second via hole that connects to the upper electrode and extends in a normal upward direction of a principal surface of the upper electrode; and a plurality of lower wiring lines that are formed under the lower electrode, in which formation areas of the first and second via holes overlap formation areas of the plurality of lower wiring lines when viewed in the normal direction of the principal surface of the upper electrode.

Abstract: A method of forming an insulating film according to one embodiment of the present invention, which is a method of forming an insulating film for use in a semiconductor device, performs thermal oxidation of a tantalum nitride film at a temperature range of 200 to 400 degrees centigrade by a wet oxidation process, whereby a tantalum oxide film is formed as the insulating film.