Patents by Inventor Takayuki Kawahara

Takayuki Kawahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110128780
    Abstract: At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
    Type: Application
    Filed: February 9, 2011
    Publication date: June 2, 2011
    Inventors: Kenichi OSADA, Naoki Kitai, Takayuki Kawahara, Kazumasa Yanagisawa
  • Publication number: 20110122681
    Abstract: An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode. Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area. Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.
    Type: Application
    Filed: February 4, 2011
    Publication date: May 26, 2011
    Inventors: Masanao YAMAOKA, Takayuki Kawahara
  • Patent number: 7943996
    Abstract: The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: May 17, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Kawahara, Masanao Yamaoka
  • Publication number: 20110102019
    Abstract: Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate.
    Type: Application
    Filed: January 10, 2011
    Publication date: May 5, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenichi OSADA, Takayuki KAWAHARA, Masanao YAMAOKA
  • Publication number: 20110103136
    Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
    Type: Application
    Filed: November 3, 2010
    Publication date: May 5, 2011
    Inventors: Satoru Akiyama, Riichiro Takemura, Takayuki Kawahara, Tomonori Sekiguchi
  • Patent number: 7907435
    Abstract: At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: March 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Osada, Naoki Kitai, Takayuki Kawahara, Kazumasa Yanagisawa
  • Publication number: 20100327356
    Abstract: The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits. having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.
    Type: Application
    Filed: September 2, 2010
    Publication date: December 30, 2010
    Inventors: Takayuki KAWAHARA, Masanao YAMAOKA
  • Patent number: 7843751
    Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: November 30, 2010
    Assignee: Hitachi, Ltd
    Inventors: Satoru Akiyama, Riichiro Takemura, Takayuki Kawahara, Tomonori Sekiguchi
  • Patent number: 7808045
    Abstract: The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: October 5, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Kawahara, Masanao Yamaoka
  • Patent number: 7787290
    Abstract: In MRAM using a spin-transfer torque switching, a sufficient writing operation with a small memory cell is realized, and a reading current is enlarged while a reading disturbance is suppressed. In the case where the free layer of the tunnel magneto-resistance element is located on the side of the bit line, using a PMOS transistor, and in the case where the fixed layer of the tunnel magneto-resistance element is located on the side of the bit line, using an NMOS transistor, an anti-parallel writing in a source grounding operation is performed. The reading and writing operation margin is improved by performing a reading operation in an anti-parallel writing direction.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: August 31, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Riichiro Takemura, Takayuki Kawahara, Kenchi Ito, Hiromasa Takahashi
  • Publication number: 20100214833
    Abstract: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
    Type: Application
    Filed: May 5, 2010
    Publication date: August 26, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Riichiro Takemura, Kenzo Kurotsuchi, Takayuki Kawahara
  • Patent number: 7778068
    Abstract: In a memory using spin transfer torque, state of the spin is made unstable by applying a weak pulse before rewriting to reduce rewrite current. Reading of high-speed operation is performed with current in a regime where the current becomes non-linearly increases corresponding to the pulse width to suppress disturb. Further, fluctuation of respective memory cells is suppressed by a driving method setting the amount of spin constant by bit line charge to suppress read disturb.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: August 17, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Kawahara, Riichiro Takemura, Kenchi Ito, Hiromasa Takahashi
  • Publication number: 20100201429
    Abstract: The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.
    Type: Application
    Filed: April 26, 2010
    Publication date: August 12, 2010
    Inventors: Takayuki KAWAHARA, Masanao Yamaoka
  • Patent number: 7750668
    Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: July 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Masashi Horiguchi, Kunio Uchiyama, Kiyoo Itoh, Takeshi Sakata, Masakazu Aoki, Takayuki Kawahara
  • Patent number: 7742330
    Abstract: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: June 22, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Riichiro Takemura, Kenzo Kurotsuchi, Takayuki Kawahara
  • Patent number: 7738286
    Abstract: A magnetic memory device comprises a magnetic tunnel junction (MTJ) connecting to a bit line to a sense line through an isolation transistor. The MTJ includes a ferromagnetic layer having a magnetic hard axis. An assist current line overlies the bit line and is insulated from the bit line. The MTJ is switchable between a first, relatively high resistance state and a second, relatively low resistance state. The assist current line applies a magnetic field along the magnetic hard axis in the ferromagnetic layer, independently of current flow through the MTJ for assisting switching of the MTJ between the first and second states.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: June 15, 2010
    Assignees: Hitachi, Ltd., Centre National de la Recherche Scientifique, Universite Paris Sud XI
    Inventors: Kenchi Ito, Hiromasa Takahashi, Takayuki Kawahara, Riichiro Takemura, Thibault Devolder, Paul Crozat, Joo-von Kim, Claude Chappert
  • Patent number: 7732864
    Abstract: The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: June 8, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takayuki Kawahara, Masanao Yamaoka
  • Patent number: 7692943
    Abstract: A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: April 6, 2010
    Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Kenichi Osada, Takayuki Kawahara, Ken Yamaguchi, Yoshikazu Saito, Naoki Kitai
  • Publication number: 20100065911
    Abstract: An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode. Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area. Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.
    Type: Application
    Filed: November 23, 2009
    Publication date: March 18, 2010
    Inventors: Masanao YAMAOKA, Takayuki KAWAHARA
  • Publication number: 20100061169
    Abstract: An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.
    Type: Application
    Filed: November 18, 2009
    Publication date: March 11, 2010
    Inventors: Masanao YAMAOKA, Takayuki Kawahara