Patents by Inventor Takayuki Kawahara

Takayuki Kawahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7639525
    Abstract: A semiconductor memory device for reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode is provided. The semiconductor memory device also prevents an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area, and ensures stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: December 29, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Masanao Yamaoka, Takayuki Kawahara
  • Publication number: 20090310399
    Abstract: In a memory using spin transfer torque, state of the spin is made unstable by applying a weak pulse before rewriting to reduce rewrite current. Reading of high-speed operation is performed with current in a regime where the current becomes non-linearly increases corresponding to the pulse width to suppress disturb. Further, fluctuation of respective memory cells is suppressed by a driving method setting the amount of spin constant by bit line charge to suppress read disturb.
    Type: Application
    Filed: August 21, 2009
    Publication date: December 17, 2009
    Applicant: HITACHI, LTD.
    Inventors: Takayuki Kawahara, Riichiro Takemura, Kenchi ITO, Hiromasa Takahashi
  • Publication number: 20090310400
    Abstract: In MRAM using a spin-transfer torque switching, a sufficient writing operation with a small memory cell is realized, and a reading current is enlarged while a reading disturbance is suppressed. In the case where the free layer of the tunnel magneto-resistance element is located on the side of the bit line, using a PMOS transistor, and in the case where the fixed layer of the tunnel magneto-resistance element is located on the side of the bit line, using an NMOS transistor, an anti-parallel writing in a source grounding operation is performed. The reading and writing operation margin is improved by performing a reading operation in an anti-parallel writing direction.
    Type: Application
    Filed: August 21, 2009
    Publication date: December 17, 2009
    Applicant: HITACHI, LTD.
    Inventors: Riichiro Takemura, Takayuki Kawahara, Kenchi Ito, Hiromasa Takahashi
  • Patent number: 7633315
    Abstract: An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: December 15, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Masanao Yamaoka, Takayuki Kawahara
  • Patent number: 7609545
    Abstract: To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.
    Type: Grant
    Filed: July 26, 2008
    Date of Patent: October 27, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kenichi Osada, Takayuki Kawahara
  • Patent number: 7609544
    Abstract: The present invention provides a technology which can suppress a variation in a value after a write operation to minimum so as to facilitate multi-bit operation in a semiconductor device such as a phase change memory. A semiconductor device includes: a memory cell having a storage element (phase change material) that stores information depending on a state change by temperature; an I/O circuit; and means which, when writing data, performs a set operation and an operation for writing desired data, measures a resistance value of the storage element by means of a verify operation, and when the resistance value is not within a target range, performs the set operation and the write operation again while changing a voltage to be applied to the storage element.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: October 27, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kenichi Osada, Takayuki Kawahara
  • Patent number: 7596014
    Abstract: In a memory using spin transfer torque, state of the spin is made unstable by applying a weak pulse before rewriting to reduce rewrite current. Reading of high-speed operation is performed with current in a regime where the current becomes non-linearly increases corresponding to the pulse width to suppress disturb. Further, fluctuation of respective memory cells is suppressed by a driving method setting the amount of spin constant by bit line charge to suppress read disturb.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: September 29, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Kawahara, Riichiro Takemura, Kenchi Ito, Hiromasa Takahashi
  • Patent number: 7593253
    Abstract: In MRAM using a spin-transfer torque switching, a sufficient writing operation with a small memory cell is realized, and a reading current is enlarged while a reading disturbance is suppressed. In the case where the free layer of the tunnel magneto-resistance element is located on the side of the bit line, using a PMOS transistor, and in the case where the fixed layer of the tunnel magneto-resistance element is located on the side of the bit line, using an NMOS transistor, an anti-parallel writing in a source grounding operation is performed. The reading and writing operation margin is improved by performing a reading operation in an anti-parallel writing direction.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: September 22, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Riichiro Takemura, Takayuki Kawahara, Kenchi Ito, Hiromasa Takahashi
  • Publication number: 20090180343
    Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
    Type: Application
    Filed: January 12, 2009
    Publication date: July 16, 2009
    Inventors: Satoru AKIYAMA, Riichiro TAKEMURA, Takayuki KAWAHARA, Tomonori SEKIGUCHI
  • Publication number: 20090129142
    Abstract: A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.
    Type: Application
    Filed: January 22, 2009
    Publication date: May 21, 2009
    Inventors: Masanao Yamaoka, Kenichi Osada, Kiyoo Itoh, Takayuki Kawahara
  • Patent number: 7511558
    Abstract: A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: March 31, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoo Itoh, Ryuta Tsuchiya, Takayuki Kawahara
  • Publication number: 20090073753
    Abstract: At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
    Type: Application
    Filed: September 21, 2005
    Publication date: March 19, 2009
    Inventors: Kenichi Osada, Naoki Kitai, Takayuki Kawahara, Kazumasa Yanagisawa
  • Patent number: 7498637
    Abstract: A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: March 3, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Masanao Yamaoka, Kenichi Osada, Kiyoo Itoh, Takayuki Kawahara
  • Patent number: 7492655
    Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: February 17, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Akiyama, Riichiro Takemura, Takayuki Kawahara, Tomonori Sekiguchi
  • Publication number: 20090016102
    Abstract: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.
    Type: Application
    Filed: May 9, 2008
    Publication date: January 15, 2009
    Inventors: Yusuke Jyouno, Takayuki Kawahara, Katsutaka Kimura
  • Patent number: 7463533
    Abstract: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: December 9, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hideaki Kurata, Naoki Kobayashi, Shunichi Saeki, Takashi Kobayashi, Takayuki Kawahara, Yoshinori Takase, Keiichi Yoshida, Michitaro Kanamitsu, Shoji Kubono, Atsushi Nozoe
  • Publication number: 20080285336
    Abstract: To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.
    Type: Application
    Filed: July 26, 2008
    Publication date: November 20, 2008
    Inventors: KENICHI OSADA, Takayuki Kawahara
  • Patent number: 7443718
    Abstract: A magnetic memory device comprises a magnetic tunnel junction (MTJ) having a ferromagnetic free layer, and exhibits a first, relatively high resistance state, and a second, relatively low resistance state. To write to the magnetic memory device a current IMTJ is driven through the MTJ. For a first duration, the current is equal to a DC threshold current, being the DC current required to switch the multilayer structure between the first state and the second state. This induces a C-like domain structure in the free layer. For a second duration, the current IMTJ is larger than the DC threshold current. This causes the MTJ to switch states. The current requited to cause switching is less than that required using a uniform current pulse.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: October 28, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Kenchi Ito, Hiromasa Takahashi, Takayuki Kawahara, Riichiro Takemura
  • Patent number: 7420838
    Abstract: To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: September 2, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kenichi Osada, Takayuki Kawahara
  • Publication number: 20080203403
    Abstract: The semiconductor integrated circuit (1) has a memory (4) and a logic circuit (5), which are mixedly palletized on a silicon substrate (2). The memory includes a partially-depleted type nMOS (6) having an SOI structure and formed on UTB (3). The partially-depleted type nMOS has a backgate region (14) under UTB, to which a voltage can be applied independently of a corresponding gate terminal. The logic circuit includes an nMOS (7) and a pMOS (8), and both are of a fully-depleted type, formed on UTB and have an SOI structure.
    Type: Application
    Filed: December 19, 2007
    Publication date: August 28, 2008
    Inventors: Takayuki Kawahara, Masanao Yamaoka, Nobuyuki Sugii