Patents by Inventor Takayuki Tani

Takayuki Tani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210278433
    Abstract: The purpose of the present invention is to provide a method for manufacturing a three-dimensionally structured member which can be made by a simpler process. The method for manufacturing a three-dimensionally structured member includes shaping a flat plate-shaped base member to produce a three-dimensionally structured member having a plurality of sections that are different from one another in thickness. The manufacturing method comprises: a mask formation step for forming a mask over the whole of at least one main surface of the base member; a mask removal step for removing a part of the mask; and an etching step for etching an exposed part of the base member, wherein a combination of the mask removal step and the etching step is performed on the mask and the base member that correspond to each of the plurality of sections of the three-dimensionally structured member, in the order from thinnest to the thickest of thicknesses of the three-dimensionally structured members.
    Type: Application
    Filed: July 16, 2019
    Publication date: September 9, 2021
    Inventors: Kazuaki TANI, Takayoshi YAMAGUCHI, Takayuki TAMAKI
  • Publication number: 20200144038
    Abstract: A treatment method performed by a film processing apparatus including: a first discharge electrode unit and a second discharge electrode unit respectively including magnets that form a magnetic field; and an AC power source capable of alternately switching polarities of the first discharge electrode unit and the second discharge electrode unit. In the treatment method, a predetermined surface treatment of a film F is performed by generating a plasma P while alternately switching polarities of the first discharge electrode unit and the second discharge electrode unit by using high-frequency power supplied from the AC power source.
    Type: Application
    Filed: December 27, 2019
    Publication date: May 7, 2020
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Kengo OKAMURA, Ken TAKAHARA, Takahiro HAYAKAWA, Michihiro HANAMI, Takayuki TANI
  • Publication number: 20190087530
    Abstract: A method for designing the cross-sectional shape of the fuselage of a flying body having the fuselage extending in the roll axial direction, the section being taken on a plane perpendicular to the roll axial direction. This method is provided with: an initial setting step S12 for setting an initial cross-sectional shape, which is the initial cross-sectional shape of the fuselage having a cross-sectional shape that is not truly circular; load application steps S14, S21, S28 for analytically or experimentally preloading the fuselage having the initial cross-sectional shape; and a design shape setting step S17 for acquiring the cross-sectional shape of the preloaded fuselage as the design cross-sectional shape of the fuselage.
    Type: Application
    Filed: April 20, 2017
    Publication date: March 21, 2019
    Inventors: Shunichi MORISHIMA, Masatake HATANO, Kiyoshi SUGETA, Toshio KOZASA, Timothy Craig MOMOSE, Takayuki TANI, Hitoshi OJIKA, Masahiko MATSUHASHI, Toshihiko AZUMA
  • Publication number: 20090166334
    Abstract: A microshaft forming method and apparatus for forming a microshaft without requiring high level of stillness required by conventional methods. The microshaft forming apparatus comprises an elongated electrode (1) to be formed into a microshaft, a forming plate (3) for forming the electrode (1), electrode rotating means for rotating the electrode (1) around the length direction (1a) of the electrode (1), a discharge machining power supply (5) for applying a voltage between the electrode (1) and the forming plate (3) to cause discharge between the electrode (1) and the forming plate (3), and electrode moving means for traversing the electrode (1) rotated by the electrode rotating means across the forming plate (3) from the side edge surface (3a) of the forming plate (3).
    Type: Application
    Filed: November 9, 2006
    Publication date: July 2, 2009
    Applicants: The University of Tokyo, National University Corporation Tsukuba University of Technology
    Inventors: Naotake Mohri, Takayuki Tani
  • Publication number: 20080261008
    Abstract: An anti-reflection film, including: a transparent base film; and an anti-reflection stacked member provided on the hard coating, having, in alternation, a high-refractivity oxide thin film layer and a low-refractivity oxide thin film layer, wherein: an outermost layer of the anti-reflection stacked member is the low-refractivity oxide thin film layer; the low-refractivity oxide thin film layer is a silicon oxide thin film; a thickness of the silicon oxide thin film is in a range of 75 nm or greater, and 100 nm or smaller; the silicon oxide thin film has a first layer on a side of the transparent base film, and a second layer on an outside of the first layer; and a composition ratio Si/O (A) of silicon to oxygen in the first layer and a composition ratio Si/O (B) of silicon to oxygen in the second layer satisfies a relationship, Si/O (A)>Si/O (B).
    Type: Application
    Filed: April 16, 2008
    Publication date: October 23, 2008
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Kazutoshi Kiyokawa, Yuki Watanabe, Takayuki Tani, Yasunori Kurauchi
  • Patent number: 6919624
    Abstract: It is difficult to check the mounted state of solder by means of visual inspection after the mounting of a semiconductor device according to a conventional art, in particular, a CSP-semiconductor device, to a substrate and a problem arises wherein defective products increase and yield decreases. Terminals 50, 51, 52 and 53 for external connection are exposed from second main surface 412 of first insulating substrate 41 in the semiconductor device according to the present invention. Thus, second insulating substrate 48 is adhered to second main surface 412 so as to surround the internal portions of these terminals for external connection. Thereby, second insulating substrate 48 serves as a background mirror so that the mounted state of deep portions of the solder can be ascertained at the time of visual inspection of the mounted state of solder after the mounting of the semiconductor device to the substrate.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: July 19, 2005
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Takayuki Tani, Takao Shibuya
  • Patent number: 6911353
    Abstract: A lead frame has an array of mounting portions connected by joint bars, and each of the mounting portions has an island serving as an external connection terminal and a plurality of lead terminals extending from the island and serving as external connection terminals for a semiconductor chip to be mounted on an adjacent island along the array. An electrically conductive paste is applied to the island, and a semiconductor chip is mounted on the island. Then, the semiconductor chip is electrically connected to the lead terminals by wires. A resin layer is deposited over the semiconductor chip, a principal surface of the island, and principle surfaces the lead terminals, while leaving opposite surfaces of the island and the lead terminals exposed. A region surrounding the island and the lead terminals electrically connected to the island is cut off into a package.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: June 28, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takayuki Tani, Takashi Sekibata, Haruo Hyodo
  • Patent number: 6784523
    Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area. Another object of the present invention is to provide a method of fabricating a semiconductor device relatively inexpensively. An insulating board with a plurality of device carrier areas thereon is prepared, and islands and leads are formed on the device carrier areas electrically connected via through holes to external electrodes on the back of the insulating board. The external electrodes are spaced or retracted inwardly from edges of the device carrier areas. Semiconductor chips are mounted on the respective device carrier areas by die bonding and wire bonding, and then covered with a common resin layer. The resin layer and the insulating board are separated along cutting lines into segments including the device carrier areas thereby to produce individual semiconductor devices.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: August 31, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takayuki Tani, Haruo Hyoudo, Takao Shibuya
  • Patent number: 6737285
    Abstract: The present invention provides a method for manufacturing a semiconductor device comprising steps of: bonding one semiconductor chip to each of multiple mounting portions of a substrate; covering the semiconductor chips bonded to the mounting portions with a common resin layer; bringing the substrate into contact with the resin layer and gluing the substrate to an adhesive sheet; and performing dicing and measurement for the semiconductor chips that are glued to the adhesive sheet.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: May 18, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Koji Iketani, Takayuki Tani, Takao Shibuya, Haruo Hyodo
  • Publication number: 20040070067
    Abstract: It is difficult to check the mounted state of solder by means of visual inspection after the mounting of a semiconductor device according to a conventional art, in particular, a CSP-semiconductor device, to a substrate and a problem arises wherein defective products increase and yield decreases. Terminals 50, 51, 52 and 53 for external connection are exposed from second main surface 412 of first insulating substrate 41 in the semiconductor device according to the present invention. Thus, second insulating substrate 48 is adhered to second main surface 412 so as to surround the internal portions of these terminals for external connection. Thereby, second insulating substrate 48 serves as a background mirror so that the mounted state of deep portions of the solder can be ascertained at the time of visual inspection of the mounted state of solder after the mounting of the semiconductor device to the substrate.
    Type: Application
    Filed: August 28, 2003
    Publication date: April 15, 2004
    Inventors: Takayuki Tani, Takao Shibuya
  • Patent number: 6511864
    Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area. An insulating board with a plurality of device carrier areas thereon is prepared, and semiconductor chips are mounted on the respective device carrier areas and then covered with a common resin layer. The resin layer and said insulating board are separated along dicing lines into segments including the device carrier areas thereby to produce individual semiconductor devices. External electrodes connected to electrodes of the semiconductor chips are mounted on the back of the insulating board. The external electrodes are positioned symmetrically with respect to central lines of the packaged semiconductor device for preventing various problems which would otherwise be caused when such a small package is mounted.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: January 28, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Haruo Hyoudo, Takayuki Tani, Takao Shibuya
  • Patent number: 6451628
    Abstract: An object of the present invention is to provide a method of manufacturing a semiconductor device which enables a decrease in mounting area on a printed circuit board and an increase in space efficiency on the printed circuit board.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: September 17, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takayuki Tani, Takao Shibuya, Haruo Hyodo
  • Publication number: 20020119603
    Abstract: A lead frame has an array of mounting portions connected by joint bars, and each of the mounting portions has an island serving as an external connection terminal and a plurality of lead terminals extending from the island and serving as external connection terminals for a semiconductor chip to be mounted on an adjacent island along the array. An electrically conductive paste is applied to the island, and a semiconductor chip is mounted on the island. Then, the semiconductor chip is electrically connected to the lead terminals by wires. A resin layer is deposited over the semiconductor chip, a principal surface of the island, and principle surfaces the lead terminals, while leaving opposite surfaces of the island and the lead terminals exposed. A region surrounding the island and the lead terminals electrically connected to the island is cut off into a package.
    Type: Application
    Filed: May 2, 2002
    Publication date: August 29, 2002
    Inventors: Takayuki Tani, Takashi Sekibata, Haruo Hyodo
  • Publication number: 20020081769
    Abstract: The object of the present invention is to provide a semiconductor device having small mounting area with reduced cost.
    Type: Application
    Filed: February 25, 2002
    Publication date: June 27, 2002
    Inventors: Takayuki Tani, Haruo Hyoudo, Takao Shibuya
  • Patent number: 6410363
    Abstract: A lead frame has an array of mounting portions connected by joint bars, and each of the mounting portions has an island serving as an external connection terminal and a plurality of lead terminals extending from the island and serving as external connection terminals for a semiconductor chip to be mounted on an adjacent island along the array. An electrically conductive paste is applied to the island, and a semiconductor chip is mounted on the island. Then, the semiconductor chip is electrically connected to the lead terminals by wires. A resin layer is deposited over the semiconductor chip, a principal surface of the island, and principle surfaces the lead terminals, while leaving opposite surfaces of the island and the lead terminals exposed. A region surrounding the island and the lead terminals electrically connected to the island is cut off into a package.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: June 25, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takayuki Tani, Takashi Sekibata, Haruo Hyodo
  • Patent number: 6368893
    Abstract: A method of fabricating a semiconductor device including preparing a board with a plurality of device carrier areas thereon and an electrode pattern serving as external electrodes on a back of the board. Semiconductor chips are fixed respectively to the device carrier areas. The semiconductor chips fixed to the device carrier areas are covered with a common resin layer. A round surface of the common resin layer is flattened into a flat and horizontal surface, and a dicing sheet is applied to the flat and horizontal surface of the common resin layer with electrode pattern facing upwardly. The board and the common resin layer are separated into segments including the device carrier areas thereby to produce individual semiconductor devices by dicing from the back of the board.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: April 9, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takayuki Tani, Haruo Hyoudo, Takao Shibuya
  • Publication number: 20020022302
    Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area.
    Type: Application
    Filed: August 28, 2001
    Publication date: February 21, 2002
    Inventors: Haruo Hyoudo, Takayuki Tani, Takao Shibuya
  • Publication number: 20020022312
    Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area. Another object of the present invention is to provide a method of fabricating a semiconductor device relatively inexpensively. An insulating board with a plurality of device carrier areas thereon is prepared, and islands and leads are formed on the device carrier areas electrically connected via through holes to external electrodes on the back of the insulating board. The external electrodes are spaced or retracted inwardly from edges of the device carrier areas. Semiconductor chips are mounted on the respective device carrier areas by die bonding and wire bonding, and then covered with a common resin layer. The resin layer and the insulating board are separated along cutting lines into segments including the device carrier areas thereby to produce individual semiconductor devices.
    Type: Application
    Filed: October 12, 2001
    Publication date: February 21, 2002
    Inventors: Takayuki Tani, Haruo Hyoudo, Takao Shibuya
  • Publication number: 20020004250
    Abstract: The present invention provides a method for manufacturing a semiconductor device comprising steps of: bonding one semiconductor chip to each of multiple mounting portions of a substrate; covering the semiconductor chips bonded to the mounting portions with a common resin layer; bringing the substrate into contact with the resin layer and gluing the substrate to an adhesive sheet; and performing dicing and measurement for the semiconductor chips that are glued to the adhesive sheet.
    Type: Application
    Filed: July 6, 2001
    Publication date: January 10, 2002
    Inventors: Koji Iketani, Takayuki Tani, Takao Shibuya, Haruo Hyodo
  • Patent number: 6326232
    Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area. Another object of the present invention is to provide a method of fabricating a semiconductor device relatively inexpensively. An insulating board with a plurality of device carrier areas thereon is prepared, and islands and leads are formed on the device carrier areas electrically connected via through holes to external electrodes on the back of the insulating board. The external electrodes are spaced or retracted inwardly from edges of the device carrier areas. Semiconductor chips are mounted on the respective device carrier areas by die bonding and wire bonding, and then covered with a common resin layer. The resin layer and the insulating board are separated along cutting lines into segments including the device carrier areas thereby to produce individual semiconductor devices.
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: December 4, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takayuki Tani, Haruo Hyoudo, Takao Shibuya