Patents by Inventor Takenori Sonoda

Takenori Sonoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190227359
    Abstract: A reliability of seal portion of a liquid crystal display device can be improved by the following structure. A liquid crystal display device includes: a TFT substrate which includes a display region and a terminal part, and has an inorganic insulating film formed on an organic passivation film and an alignment film formed over the inorganic insulating film; a counter substrate, the TFT substrate and the counter substrate bonded together by a sealing material formed at a seal part surrounding the display region; and a liquid crystal sealed inside. At the seal part, a transparent conductive oxide film is formed between the inorganic insulating film and the alignment film. The transparent conductive oxide film exists inside an edge of the TFT substrate and hence, the edge of the TFT substrate is free of the transparent conductive oxide film.
    Type: Application
    Filed: April 3, 2019
    Publication date: July 25, 2019
    Inventors: Takenori HIROTA, Yasuhiro KANAYA, Hidehiro SONODA, Toshiki KANEKO
  • Patent number: 10288945
    Abstract: A reliability of seal portion of a liquid crystal display device can be improved by the following structure. A liquid crystal display device includes: a TFT substrate which includes a display region and a terminal part, and has an inorganic insulating film formed on an organic passivation film and an alignment film formed over the inorganic insulating film; a counter substrate, the TFT substrate and the counter substrate bonded together by a sealing material formed at a seal part surrounding the display region; and a liquid crystal sealed inside. At the seal part, a transparent conductive oxide film is formed between the inorganic insulating film and the alignment film. The transparent conductive oxide film exists inside an edge of the TFT substrate and hence, the edge of the TFT substrate is free of the transparent conductive oxide film.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: May 14, 2019
    Assignee: Japan Display Inc.
    Inventors: Takenori Hirota, Yasuhiro Kanaya, Hidehiro Sonoda, Toshiki Kaneko
  • Patent number: 5537537
    Abstract: A hard disc drive includes a self-diagnostic program which is stored either in ROM, on the magnetic disc or the like. This program enables the disc drive to be placed in an environment wherein a predetermined temperature is maintained and a so called "burn in" diagnostic carried out without the need for host computers and interface cabling. The outcome of the diagnostic can be recorded on a suitable media within the drive for later accessing.
    Type: Grant
    Filed: July 26, 1995
    Date of Patent: July 16, 1996
    Assignee: Sony Corporation
    Inventors: Daisuke Fujikawa, Takenori Sonoda, Kenichi Sakai
  • Patent number: 4520407
    Abstract: An apparatus for recording and/or reproducing a digital signal made up of a plurality of channel signals digitally recorded in respective tracks on a magnetic record medium comprises a reproducing circuit which reproduces the channel signals recorded in the respective tracks, a recording circuit associated with the tracks which records digital signals in the tracks, and a selector circuit which selectively supplies the reproduced channel signals to the recording circuit for digital recording by the latter in at least a selected one of the tracks on the magnetic record medium.
    Type: Grant
    Filed: February 10, 1983
    Date of Patent: May 28, 1985
    Assignee: Sony Corporation
    Inventors: Masato Tanaka, Takenori Sonoda
  • Patent number: 4441184
    Abstract: A PCM digital signal is provided with double-interleaving and error-correction encoding to protect against errors occurring during transmission, which can be carried out by magnetic recording and reproducing. The PCM signal is processed as error correcting blocks of several data word sequences and an associated error correction word sequence, and the double-interleaved sequences are then transmitted as transmission blocks. Up to one erroneous word in each error correction block can be corrected by using the error correction word sequence. Any uncorrectable word can be compensated by substituting a synthetic word interpolated from immediately preceding and following data words known to be correct. The distance between successive data words is made as great as possible so that a long burst error is unlikely to affect the ability to compensate uncorrectable errors.
    Type: Grant
    Filed: August 7, 1981
    Date of Patent: April 3, 1984
    Assignee: Sony Corporation
    Inventors: Takenori Sonoda, Nobuhiko Watanabe, Masato Tanaka
  • Patent number: 4429390
    Abstract: A digital signal is encoded for error correction, and the encoded digital signal is transmitted in M transmitting paths. The signal to be encoded occurs as N sequences of data words. A plurality n of sequences of error correcting words are generated from respective words of the N sequences delayed by respective different delay times of (D-di) words, where d.sub.i is a whole number associated with an ith one of the n error correcting word sequences. The resulting N data word sequences and n error correcting word sequences are provided with respective different total delay times, so that the total delays of the N sequences differ by an integral number D of words from one another. Blocks of the delayed N data sequences and n error correcting word sequences are formed and the blocks are cyclically distributed among the M transmitting paths. The values of M, N, n, D, and d.sub.i are selected so that the least common multiple of any two values of (d-d.sub.
    Type: Grant
    Filed: August 7, 1981
    Date of Patent: January 31, 1984
    Assignee: Sony Corporation
    Inventors: Takenori Sonoda, Nobuhiko Watanabe, Masato Tanaka
  • Patent number: 4402021
    Abstract: At least one channel of digitized information is recorded in at least one data track on a record medium by forming data blocks, each containing a predetermined number of data words representing the digitized information, and recording successive data blocks in at least one data track. A block address also is generated to identify each of the respective data blocks, this block address also being recorded with the data block in the data track. A predetermined number of successive data blocks is recorded in the data track in a sector interval. A control signal having at least a sector address for identifying the sector interval also is generated, and this control signal is recorded in a separate control track, successive control signals being recorded in successive sector intervals. The least significant bit of the sector address is coincident with the most significant bit of the block address, such that the block address is repeated with a periodicity related to the sector interval.
    Type: Grant
    Filed: August 5, 1981
    Date of Patent: August 30, 1983
    Assignee: Sony Corporation
    Inventors: Takenori Sonoda, Nobuhiko Watanabe, Masato Tanaka
  • Patent number: 4389681
    Abstract: At least one channel of digitized information is recorded in a selected number of data tracks by a record medium. The digitized information is encoded, modulated and then recorded in a predetermined number of tracks. For example, if n channels of digitized information are to be recorded in m data tracks, then each channel is recorded in m/n data tracks (m.gtoreq.n). A control signal is generated to include control data representing at least one of the following: (a) the number of data tracks in which each channel of digitized information is recorded, (b) the encoding scheme used to encode the information, (c) the type of modulation used to modulate the encoded information and (d) the relative speed of movement of the record medium. The control signal is recorded in a separate control track. Thus, the control signal represents the particular format in which the digitized information is recorded.
    Type: Grant
    Filed: July 27, 1981
    Date of Patent: June 21, 1983
    Assignee: Sony Corporation
    Inventors: Masato Tanaka, Takenori Sonoda, Nobuhiko Watanabe
  • Patent number: 4348699
    Abstract: An apparatus for recording and/or reproducing a serial digitized analog signal controls the transport speed of a recording medium according to the sampling rate employed in digitizing the analog signal to produce a constant data density on the recording medium regardless of the sampling rate selected. The frequency of a fundamental clock signal establishes the sampling frequency during recording. A coded timing signal also recorded on the recording medium includes both a sync signal and a coded identity of the sampling frequency in use. During reproduction, the coded identity of the sampling frequency is used to select the same fundamental clock signal as was used during recording and the reproduced sync signal is phase compared with a reference signal derived from the fundamental clock signal to correspondingly control the speed and phase of transport of the recording medium. The fundamental clock signal may be manually varied during reproduction for pitch control of the reproduced analog signal.
    Type: Grant
    Filed: May 13, 1980
    Date of Patent: September 7, 1982
    Assignee: Sony Corporation
    Inventors: Yoshikazu Tsuchiya, Masato Tanaka, Takenori Sonoda, Tetsu Watanabe, Chiaki Kanai, Nobuhiko Watanabe
  • Patent number: 3981006
    Abstract: An amplitude adjustment circuit transmits an analog signal to an analog-to-digital converter. If the resulting digital signal reaches the maximum permissible digital value, a monostable control circuit is triggered to cause the amplitude adjustment circuit to reduce the level of the analog signal a certain amount. If the digital signal again reaches the maximum permissible digital value before the control circuit returns to its stable condition a second monostable circuit is triggered (and the first one is retriggered) to cause the amplitude adjustment circuit to reduce the level of the analog signal another amount. The unstable interval for the second monostable circuit is shorter than for the first, and, in the absence of further triggering, both such circuits return to their stable states in succession. The digital signals are used to reconstruct the analog signal in apparatus similar to the encoding apparatus and including amplitude adjustment apparatus controlled by the amplitude compression signals.
    Type: Grant
    Filed: June 21, 1974
    Date of Patent: September 14, 1976
    Assignee: Sony Corporation
    Inventors: Jun Takayama, Takenori Sonoda, Shoichi Nakamura
  • Patent number: 3981005
    Abstract: A signal conversion system in which an analog signal of a certain magnitude can be encoded as a digital signal making full use of the available number of bits of an A/D converter. The system includes amplitude adjustment apparatus with an up-down counter actuated by the maximum available binary value of the digital signal to count UP one step and set an amplitude selection circuit to effectively attenuate the amplitude of the analog signal by a predetermined amount. The counter may have more than one memorizable count level to control a corresponding number of amplitude selection levels. The counter counts DOWN when the most significant bit of the digital signal drops from 1 to 0. The invention includes a corresponding analog signal reconstruction circuit except that it includes a D/A converter that produces an analog signal at maximum value that must be attenuated for low-amplitude values.
    Type: Grant
    Filed: June 21, 1974
    Date of Patent: September 14, 1976
    Assignee: Sony Corporation
    Inventors: Jun Takayama, Takenori Sonoda
  • Patent number: 3968328
    Abstract: In dynamic modulation (D.M.) of non-return-to-zero pulse signals, the only condition under which the D.M. signal would remain in the same state, either 1 or 0, for two consecutive pulse intervals is when the NRZ signal includes the sequence 101. Two sampling signals at the proper clock repetition rate are generated from the D.M. signal by the decoder and are successively used to sample the D.M. signal and to sample the signal resulting from the first sampling. Information of the state of the D.M. signal at the time of the first sampling is retained to be compared with the state of the D.M. signal at a later time, and the state of one of the compared signals is separately compared with the state of a signal between the first-compared signals. If the wrong clock pulses midway between the correct clock pulses are used in making the comparisons, a correction signal will be generated in the last half of the second consecutive pulse interval in which the D.M. signal remains in the same state.
    Type: Grant
    Filed: December 18, 1974
    Date of Patent: July 6, 1976
    Assignee: Sony Corporation
    Inventors: Yoshikazu Tsuchiya, Takenori Sonoda, Jun Takayama