Patents by Inventor Takeo Furuhata

Takeo Furuhata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200295053
    Abstract: The disclosure relates to a (thin-film transistor) TFT substrate that includes a light shielding film provided continuously adjacent to a common electrode in a region overlapping with a drain electrode in plan view below a drain electrode. Furthermore, the TFT substrate includes a light shielding film provided below the source electrode in a region where the source electrode and the common electrode overlap in plan view. In addition, in a gate terminal portion, the TFT substrate includes a light shielding film having conductivity above a gate electrode. The light shielding film is electrically connected to the gate electrode, and overlaps with the gate electrode in plan view.
    Type: Application
    Filed: November 6, 2017
    Publication date: September 17, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroya YAMARIN, Takeo FURUHATA, Kazunori INOUE
  • Patent number: 10720374
    Abstract: A semiconductor substrate according to the present invention includes a nitride semiconductor layer 203, an amorphous semiconductor layer 205 formed on one main surface side of the nitride semiconductor layer 203, a high-roughness layer 206 which is a semiconductor layer formed on the amorphous semiconductor layer 205 and has a surface roughness larger than the amorphous semiconductor layer 205, and a diamond layer 207 formed on the high-roughness layer 206. Damage to the nitride semiconductor layer can be reduced in forming the diamond layer on the nitride semiconductor layer and adhesion between the layers can be increased.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: July 21, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tomohiro Shinagawa, Takeo Furuhata, Shingo Tomohisa
  • Patent number: 10651278
    Abstract: An object is to provide a technology capable of suppressing a crack of a crystalline nitride layer which is generated due to a stress caused by difference in thermal expansion coefficients between a crystalline nitride and diamond. A semiconductor device includes a crystalline nitride layer, a structure containing silicon, and a diamond layer. The structure is disposed on a first main surface of the crystalline nitride layer. The diamond layer is disposed at least on a lateral portion of the structure and has a void between the diamond layer and the first main surface of the crystalline nitride layer. The void is a stress absorbing space, for example.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: May 12, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takeo Furuhata, Tomohiro Shinagawa
  • Publication number: 20200044090
    Abstract: The purpose of the present invention is to provide a technique with which it is possible to suppress light having a harmful wavelength from reaching an active layer. A thin film transistor substrate includes: an active layer which is disposed on a gate insulating film, overlaps with a gate electrode in plan view, and contains an oxide semiconductor; a source electrode and a drain electrode, each connected to the active layer; a protective insulating film disposed on the active layer, the source electrode, and the drain electrode; and a pixel electrode disposed on an insulating film that includes the gate insulating film or the gate insulating film and the protective insulating film, and above the absorption layer, the pixel electrode being connected to the drain electrode.
    Type: Application
    Filed: November 15, 2017
    Publication date: February 6, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takeo FURUHATA, Toshiaki FUJINO, Kazunori INOUE
  • Publication number: 20190252288
    Abstract: A semiconductor substrate according to the present invention includes a nitride semiconductor layer 203, an amorphous semiconductor layer 205 formed on one main surface side of the nitride semiconductor layer 203, a high-roughness layer 206 which is a semiconductor layer formed on the amorphous semiconductor layer 205 and has a surface roughness larger than the amorphous semiconductor layer 205, and a diamond layer 207 formed on the high-roughness layer 206. Damage to the nitride semiconductor layer can be reduced in forming the diamond layer on the nitride semiconductor layer and adhesion between the layers can be increased.
    Type: Application
    Filed: February 3, 2017
    Publication date: August 15, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tomohiro SHINAGAWA, Takeo FURUHATA, Shingo TOMOHISA
  • Publication number: 20190067421
    Abstract: An object is to provide a technology capable of suppressing a crack of a crystalline nitride layer which is generated due to a stress caused by difference in thermal expansion coefficients between a crystalline nitride and diamond. A semiconductor device includes a crystalline nitride layer, a structure containing silicon, and a diamond layer. The structure is disposed on a first main surface of the crystalline nitride layer. The diamond layer is disposed at least on a lateral portion of the structure and has a void between the diamond layer and the first main surface of the crystalline nitride layer. The void is a stress absorbing space, for example.
    Type: Application
    Filed: June 13, 2016
    Publication date: February 28, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takeo FURUHATA, Tomohiro SHINAGAWA
  • Publication number: 20190051538
    Abstract: In a semiconductor device including a crystalline nitride layer, in which diamond is used for heat dissipation thereof, it is an object of the present invention to suppress cracking of the crystalline nitride layer. The semiconductor device includes a layered body and a heat dissipation layer. The layered body includes a crystalline nitride layer and a composite layer. The composite layer includes a non-inhibiting portion which does not inhibit diamond growth on a surface thereof and an inhibiting portion which inhibits the diamond growth on the surface. A layered body main surface of the layered body has a first region in which the non-inhibiting portion is exposed and a second region in which the inhibiting portion is exposed. The heat dissipation layer is made of diamond, opposed to the main surface, adhered to the first region, and separated from the second region with a void interposed therebetween.
    Type: Application
    Filed: March 14, 2017
    Publication date: February 14, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yasushi FUJIOKA, Takeo FURUHATA, Tomohiro SHINAGAWA, Keisuke NAKAMURA
  • Publication number: 20170301805
    Abstract: A solar cell manufacturing method including: forming, on one surface of a first conductivity-type semiconductor substrate, a first doped layer in which second conductivity-type impurities are diffused in a first concentration, and a second doped layer in which the second conductivity-type impurities are diffused in a second concentration lower than the first concentration, the second doped layer has surface roughness different from the first doped layer; and forming a metal electrode on the first doped layer to be electrically connected to the first doped layer, wherein a position of the first doped layer is detected based on a difference in light reflectance between the first and second doped layers, which results from a difference in surface roughness between the first and second doped layers, and then the metal electrode is formed in alignment with a detected position of the first doped layer.
    Type: Application
    Filed: November 16, 2015
    Publication date: October 19, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroya YAMARIN, Takayuki MORIOKA, Takeo FURUHATA
  • Patent number: 9450108
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor portion, a first oxygen-containing portion provided on the semiconductor portion, a silicon-containing portion provided on the first oxygen-containing portion, a first film provided on the silicon-containing portion and including a lamination of a first portion containing silicon and oxygen and a second portion containing silicon and nitrogen, a first high dielectric insulating portion provided on the first film and having an oxide-containing yttrium, hafnium or aluminum, a second oxygen-containing portion provided on the first high dielectric insulating portion, a second high dielectric insulating portion provided on the second oxygen-containing insulating portion and having an oxide-containing yttrium, hafnium or aluminum, a third oxygen-containing portion provided on the second high dielectric insulating portion, and a second film provided on the third oxygen-containing portion.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: September 20, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Matsuo, Masayuki Tanaka, Takeo Furuhata, Koji Nakahara
  • Patent number: 9142685
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor portion, a first oxygen-containing portion located on the semiconductor portion, a silicon-containing portion located on the first oxygen-containing portion, a first film located on the silicon-containing portion and including a lamination of a first portion containing silicon and oxygen and a second portion containing silicon and nitrogen, a first high dielectric insulating portion located on the first film and having an oxide-containing yttrium, hafnium or aluminum, a second oxygen-containing portion located on the first high dielectric insulating portion, a second high dielectric insulating portion located on the second oxygen-containing insulating portion and having an oxide-containing yttrium, hafnium or aluminum, a third oxygen-containing portion located on the second high dielectric insulating portion, and a second film located on the third oxygen-containing portion.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: September 22, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiro Matsuo, Masayuki Tanaka, Takeo Furuhata, Koji Nakahara
  • Patent number: 9117957
    Abstract: A thin-film solar battery is constructed such that it includes a translucent insulating substrate, a first transparent conductive film formed of a crystalline transparent conductive film on the translucent insulating substrate, with an uneven structure on a surface thereof, a second transparent conductive film formed of a transparent conductive film on the first transparent conductive film, with an uneven structure on a surface thereof, where the uneven structure is more gentle than the uneven structure of the first transparent conductive film, a power generation layer formed on the second transparent conductive film and having at least one crystalline layer to generate power, and a backside electrode layer formed of a light-reflective conductive film on the power generation layer. A substantially convex hollow portion projecting from the translucent insulating substrate is provided between adjacent convex portions in the uneven structure of the first transparent conductive film.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: August 25, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takeo Furuhata, Keisuke Nakamura
  • Publication number: 20150228662
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor portion, a first oxygen-containing portion provided on the semiconductor portion, a silicon-containing portion provided on the first oxygen-containing portion, a first film provided on the silicon-containing portion and including a lamination of a first portion containing silicon and oxygen and a second portion containing silicon and nitrogen, a first high dielectric insulating portion provided on the first film and having an oxide-containing yttrium, hafnium or aluminum, a second oxygen-containing portion provided on the first high dielectric insulating portion, a second high dielectric insulating portion provided on the second oxygen-containing insulating portion and having an oxide-containing yttrium, hafnium or aluminum, a third oxygen-containing portion provided on the second high dielectric insulating portion, and a second film provided on the third oxygen-containing portion.
    Type: Application
    Filed: April 27, 2015
    Publication date: August 13, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro MATSUO, Masayuki TANAKA, Takeo FURUHATA, Koji NAKAHARA
  • Publication number: 20140239379
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film. The metal oxide film has a relative permittivity of not less than 7.
    Type: Application
    Filed: May 8, 2014
    Publication date: August 28, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro MATSUO, Masayuki TANAKA, Takeo FURUHATA, Koji NAKAHARA
  • Patent number: 8742487
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer and including a first high dielectric insulating film which has a higher relative permittivity than a silicon nitride film and a second high dielectric insulating film which has a higher relative permittivity than a silicon nitride film, the first and second high dielectric insulating films being structured so that a silicon oxide film is interposed between them, a control electrode formed on the second insulation layer, a first portion formed between the charge storage layer and the second insulation layer and containing silicon and nitrogen, and a second portion containing silicon and oxygen and located between the charge storage layer and the second insulation layer.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Matsuo, Masayuki Tanaka, Takeo Furuhata, Koji Nakahara
  • Publication number: 20120234375
    Abstract: A thin film solar cell includes, on a substrate, a first electrode layer formed of a transparent conductive material, a photoelectric conversion layer, and a second electrode layer including a conductive material that reflects light. The thin film solar cell includes a plurality of unit solar battery cells divided by scribe lines. The second electrode layer and the first electrode layer of the unit solar battery cell adjacent to the second electrode layer are connected in the scribe line formed in the photoelectric conversion layer. The unit solar battery cells are electrically connected in series. The scribe lines on both sides of at least one of the unit solar battery cells are formed such that the unit solar battery cell held between the scribe lines meanders while having fixed width in a predetermined direction and have same shapes that overlap when the scribe lines translate in the predetermined direction.
    Type: Application
    Filed: April 8, 2010
    Publication date: September 20, 2012
    Applicant: Mitsubishi Electric Corporation
    Inventors: Keisuke Nakamura, Hidetada Tokioka, Takeo Furuhata
  • Publication number: 20120138146
    Abstract: A thin-film solar battery is constructed such that it includes a translucent insulating substrate, a first transparent conductive film formed of a crystalline transparent conductive film on the translucent insulating substrate, with an uneven structure on a surface thereof, a second transparent conductive film formed of a transparent conductive film on the first transparent conductive film, with an uneven structure on a surface thereof, where the uneven structure is more gentle than the uneven structure of the first transparent conductive film, a power generation layer formed on the second transparent conductive film and having at least one crystalline layer to generate power, and a backside electrode layer formed of a light-reflective conductive film on the power generation layer. A substantially convex hollow portion projecting from the translucent insulating substrate is provided between adjacent convex portions in the uneven structure of the first transparent conductive film.
    Type: Application
    Filed: April 23, 2010
    Publication date: June 7, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeo Furuhata, Keisuke Nakamura
  • Publication number: 20110298039
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film. The metal oxide film has a relative permittivity of not less than 7.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 8, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiro Matsuo, Masayuki Tanaka, Takeo Furuhata, Koji Nakahara
  • Patent number: 8008707
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film. The metal oxide film has a relative permittivity of not less than 7.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: August 30, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Matsuo, Masayuki Tanaka, Takeo Furuhata, Koji Nakahara
  • Patent number: 7679127
    Abstract: A semiconductor device including a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate; a first gate electrode layer formed on the first gate insulating film; an element isolation insulating film formed so as to isolate a plurality of the first gate electrode layers; a second gate insulating film layer formed so as to cover upper surfaces of the plurality of first gate electrode layers and the element isolation insulating films; and a second gate electrode layer formed on the second gate insulating film layer; and the second gate insulating film layer includes a NONON stacked film structure and a nitride film layer contacting the first gate electrode layer and constituting a lowermost layer of the NONON stack film structure is separated at a portion interposing the plurality of neighboring first gate electrode layers.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: March 16, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Shiozawa, Takeo Furuhata, Akiko Sekihara
  • Patent number: 7598562
    Abstract: A semiconductor device including a semiconductor substrate; an element isolation region having a trench filled with an insulating film defined on the semiconductor substrate; a memory cell transistor formed in an element forming region isolated by the element isolating regions of the semiconductor substrate; and the memory cell transistor includes a gate insulating film formed on a surface of the element forming region; a floating gate formed over the gate insulating film; an inter-gate insulating film formed integrally so as to cover the floating gate and the insulating film of the element isolation region and having high dielectric constant in a portion corresponding to the floating gate and low dielectric constant in a portion corresponding to the insulating film of the element isolation region; and a control gate stacked over the floating gate via the inter-gate insulating film.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: October 6, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Nagano, Takeo Furuhata