Patents by Inventor Takeru Matsuoka

Takeru Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180240867
    Abstract: According to an embodiment, a semiconductor device includes a semiconductor layer, a first electrode, and a first insulating film. The first electrode extends in a first direction and is provided inside the semiconductor layer. The first insulating film is provided between the semiconductor layer and the first electrode, a thickness of the first insulating film in a direction from the first electrode toward the semiconductor layer increasing in stages along the first direction. The first insulating film has three or more mutually-different thicknesses.
    Type: Application
    Filed: August 30, 2017
    Publication date: August 23, 2018
    Inventors: Shunsuke Nitta, Takeru Matsuoka, Shunsuke Katoh, Masatoshi Arai, Shinya Ozawa, Bungo Tanaka
  • Patent number: 10020391
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer; a plurality of semiconductor regions; second semiconductor region; a first electrode being positioned between the plurality of first semiconductor regions, the first electrode contacting with the semiconductor layer, each of the plurality of first semiconductor regions, and the second semiconductor region via a first insulating film; a second electrode provided below the first electrode, and contacting with the semiconductor layer via a second insulating film; an insulating layer interposed between the first electrode and the second electrode; a third electrode electrically connected to the semiconductor layer; and a fourth electrode connected to the second semiconductor region. The first electrode has a first portion and a pair of second portions. And each of the pair of second portions is provided along the first insulating film.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: July 10, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeru Matsuoka, Nobuyuki Sato, Shigeaki Hayase, Kentaro Ichinoseki
  • Patent number: 9401398
    Abstract: According to one embodiment, a semiconductor device includes: a first region including: a first semiconductor layer; a first semiconductor region; a second semiconductor region; a third semiconductor region having higher impurity concentration than the first semiconductor region; a first electrode; a second electrode; an insulating film; a third electrode; a fourth electrode, a second region including a pad electrode, and the third region including: the first semiconductor layer; the first semiconductor region; a third semiconductor region; the first electrode; the second electrode; and a first insulating layer.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: July 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeru Matsuoka, Yasuhito Saito, Seiichi Kamiyama
  • Publication number: 20150318392
    Abstract: According to one embodiment, a semiconductor device includes: a first region including: a first semiconductor layer; a first semiconductor region; a second semiconductor region; a third semiconductor region having higher impurity concentration than the first semiconductor region; a first electrode; a second electrode; an insulating film; a third electrode; a fourth electrode, a second region including a pad electrode, and the third region including: the first semiconductor layer; the first semiconductor region; a third semiconductor region; the first electrode; the second electrode; and a first insulating layer.
    Type: Application
    Filed: July 14, 2015
    Publication date: November 5, 2015
    Inventors: Takeru Matsuoka, Yasuhito Saito, Seiichiro Kamiyama
  • Patent number: 9111771
    Abstract: According to one embodiment, a semiconductor device includes: a first region including: a first semiconductor layer; a first semiconductor region; a second semiconductor region; a third semiconductor region having higher impurity concentration than the first semiconductor region; a first electrode; a second electrode; an insulating film; a third electrode; a fourth electrode, a second region including a pad electrode, and the third region including: the first semiconductor layer; the first semiconductor region; a third semiconductor region; the first electrode; the second electrode; and a first insulating layer.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: August 18, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeru Matsuoka, Yasuhito Saito, Seiichiro Kamiyama
  • Publication number: 20150069598
    Abstract: In one embodiment, a heat dissipation connector mounted on a semiconductor chip and sealed up with a molding resin along with the semiconductor chip and a lead frame includes a heat dissipation portion configured to have a block shape, and have an upper face exposed out of the molding resin. The connector further includes a connecting portion configured to extend from a first side face of the heat dissipation portion, and electrically connect an electrode arranged on the semiconductor chip to the lead frame. The heat dissipation portion and the connecting portion are integrally made of the same metal sheet.
    Type: Application
    Filed: March 6, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Tamura, Nobuyuki Sato, Nobuhiro Shingai, Shinya Ozawa, Takeru Matsuoka, Hideki Okumura
  • Publication number: 20150069592
    Abstract: In one embodiment, a semiconductor device includes a lead frame including an island portion and a terminal portion separated from the island portion. The device further includes a semiconductor chip mounted on the island portion and including an electrode. The device further includes an insulating layer disposed on the semiconductor chip and having an opening to expose at least a part of the electrode. The device further includes a connector covering the electrode exposed through the opening and electrically connecting the electrode and the terminal portion.
    Type: Application
    Filed: March 6, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koji Tamura, Nobuyuki Sato, Nobuhiro Shingai, Shinya Ozawa, Takeru Matsuoka, Hideki Okumura
  • Publication number: 20150021685
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer; a plurality of semiconductor regions; second semiconductor region; a first electrode being positioned between the plurality of first semiconductor regions, the first electrode contacting with the semiconductor layer, each of the plurality of first semiconductor regions, and the second semiconductor region via a first insulating film; a second electrode provided below the first electrode, and contacting with the semiconductor layer via a second insulating film; an insulating layer interposed between the first electrode and the second electrode; a third electrode electrically connected to the semiconductor layer; and a fourth electrode connected to the second semiconductor region. The first electrode has a first portion and a pair of second portions. And each of the pair of second portions is provided along the first insulating film.
    Type: Application
    Filed: October 9, 2014
    Publication date: January 22, 2015
    Inventors: Takeru MATSUOKA, Nobuyuki SATO, Shigeaki HAYASE, Kentaro ICHINOSEKI
  • Publication number: 20150008510
    Abstract: According to one embodiment, a semiconductor device includes: a first region including: a first semiconductor layer; a first semiconductor region; a second semiconductor region; a third semiconductor region having higher impurity concentration than the first semiconductor region; a first electrode; a second electrode; an insulating film; a third electrode; a fourth electrode, a second region including a pad electrode, and the third region including: the first semiconductor layer; the first semiconductor region; a third semiconductor region; the first electrode; the second electrode; and a first insulating layer.
    Type: Application
    Filed: September 22, 2014
    Publication date: January 8, 2015
    Inventors: Takeru Matsuoka, Yasuhito Saito, Seiichiro Kamiyama
  • Patent number: 8884362
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer; a plurality of semiconductor regions; second semiconductor region; a first electrode being positioned between the plurality of first semiconductor regions, the first electrode contacting with the semiconductor layer, each of the plurality of first semiconductor regions, and the second semiconductor region via a first insulating film; a second electrode provided below the first electrode, and contacting with the semiconductor layer via a second insulating film; an insulating layer interposed between the first electrode and the second electrode; a third electrode electrically connected to the semiconductor layer; and a fourth electrode connected to the second semiconductor region. The first electrode has a first portion and a pair of second portions. And each of the pair of second portions is provided along the first insulating film.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: November 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeru Matsuoka, Nobuyuki Sato, Shigeaki Hayase, Kentaro Ichinoseki
  • Patent number: 8872257
    Abstract: According to one embodiment, a semiconductor device includes: a first region including: a first semiconductor layer; a first semiconductor region; a second semiconductor region; a third semiconductor region having higher impurity concentration than the first semiconductor region; a first electrode; a second electrode; an insulating film; a third electrode; a fourth electrode, a second region including a pad electrode, and the third region including: the first semiconductor layer; the first semiconductor region; a third semiconductor region; the first electrode; the second electrode; and a first insulating layer.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeru Matsuoka, Yasuhito Saito, Seiichiro Kamiyama
  • Publication number: 20130113039
    Abstract: A semiconductor device provides a MOSFET having first and second regions. In the first region, a plurality of unit cells of the MOSFET device are provided. At the end of the plurality of the unit cells, a termination cell is provided. An n type layer underlies the unit cells, between the unit cells and an underlying electrode. In the unit cell region, this n doped layer is dually doped with impurities at two different densities, whereas, adjacent the termination cell, a different paradigm is provided. In one aspect, only one of the two n doped layers extends along a side of the termination cell. In a second aspect, the termination unit is in contact with an oppositely doped layer as compared to the impurities in the dual doped layer. In this way, breakdown voltage may be maintained while on-resistance is simultaneously reduced.
    Type: Application
    Filed: September 7, 2012
    Publication date: May 9, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeru MATSUOKA, Kentaro ICHINOSEKI, Shigeaki HAYASE, Nobuyuki SATO
  • Publication number: 20130069150
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer; a plurality of semiconductor regions; second semiconductor region; a first electrode being positioned between the plurality of first semiconductor regions, the first electrode contacting with the semiconductor layer, each of the plurality of first semiconductor regions, and the second semiconductor region via a first insulating film; a second electrode provided below the first electrode, and contacting with the semiconductor layer via a second insulating film; an insulating layer interposed between the first electrode and the second electrode; a third electrode electrically connected to the semiconductor layer; and a fourth electrode connected to the second semiconductor region. The first electrode has a first portion and a pair of second portions. And each of the pair of second portions is provided along the first insulating film.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 21, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeru MATSUOKA, Nobuyuki Sato, Shigeaki Hayase, Kentaro Ichinoseki
  • Patent number: 8350322
    Abstract: According to one embodiment, a semiconductor device includes a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a source region of the first conductivity type, a first and a second main electrode, trench gates, a first and a second contact region. The third semiconductor layer is provided on the second semiconductor layer provided on the first semiconductor layer. The first main electrode is electrically connected to the first semiconductor layer. The second main electrode is electrically connected to the source region provided on the third semiconductor layer. The trench gates are provided from the third semiconductor layer to the second semiconductor layer. The first and second contact regions electrically connect the second main electrode and the third semiconductor layer. An opening area of the second contact hole is smaller than that of the first contact hole.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: January 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeru Matsuoka
  • Publication number: 20110108911
    Abstract: According to one embodiment, a semiconductor device includes a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a source region of the first conductivity type, a first and a second main electrode, trench gates, a first and a second contact region. The third semiconductor layer is provided on the second semiconductor layer provided on the first semiconductor layer. The first main electrode is electrically connected to the first semiconductor layer. The second main electrode is electrically connected to the source region provided on the third semiconductor layer. The trench gates are provided from the third semiconductor layer to the second semiconductor layer. The first and second contact regions electrically connect the second main electrode and the third semiconductor layer. An opening area of the second contact hole is smaller than that of the first contact hole.
    Type: Application
    Filed: September 17, 2010
    Publication date: May 12, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Takeru Matsuoka
  • Patent number: 6888258
    Abstract: A contact and a copper interconnect line as an uppermost interconnect layer are buried in an interlayer insulating film. A pad area including aluminum alloy (such as AlCu or AlSiCu) is buried in a predetermined area of the copper interconnect line. A gold wire is bonded to the pad area.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: May 3, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Takeru Matsuoka, Noriaki Fujiki, Hiroki Takewaka
  • Publication number: 20040207085
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a copper layer by plating, forming a defect trapping film on the copper layer, moving a defect in the copper layer into the defect trapping film by annealing or the like, and removing the defect trapping film. Thereby, a semiconductor device in which concentration of micro-voids in a portion in proximity to a bottom of a via due to stress migration can be restrained and a method of manufacturing the same can be obtained.
    Type: Application
    Filed: February 27, 2004
    Publication date: October 21, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Yasuhisa Fujii, Takao Kamoshima, Takeru Matsuoka
  • Publication number: 20040183197
    Abstract: A contact (15) and a copper interconnect line (16) as an uppermost interconnect layer are buried in an interlayer insulating film (14). A pad area (17) including aluminum alloy (such as AlCu or AlSiCu) is buried in a predetermined area of the copper interconnect line (16). A gold wire (18) is bonded to the pad area (17).
    Type: Application
    Filed: June 26, 2003
    Publication date: September 23, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Takeru Matsuoka, Noriaki Fujiki, Hiroki Takewaka
  • Publication number: 20040157424
    Abstract: An AlCu alloy interconnect line (100) including a TiN barrier layer (110), a lower Ti metal layer (120), an AlCu layer (130) and a TiN cap layer (140) is formed on a plasma oxide film formed on a semiconductor substrate in which devices are formed. Heat treatment is conducted to cause Al contained in the AlCu layer (130) and Ti contained in the lower Ti metal layer (120) to react with each other, thereby forming a lower AlTi alloy layer (150) in a lower portion of the AlCu layer (130). A via hole (170) is thereafter formed. A current path extending from the via hole (170) to reach the lower AlTi alloy layer (150) is ensured without passing through the AlCu layer (130), allowing electromigration resistance to be improved.
    Type: Application
    Filed: June 26, 2003
    Publication date: August 12, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Yoshihiro Kusumi, Takeru Matsuoka, Shoichi Fukui
  • Publication number: 20040130033
    Abstract: A semiconductor device has a substrate 1, a metal wiring 3 formed on the substrate 1 and covered with the films of a high-melting-point metal 2 and 4 immediately above and below and an interlayer insulating film 5 formed by a plasma CVD method so as to cover the metal wiring 3.
    Type: Application
    Filed: October 6, 2003
    Publication date: July 8, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Takeshi Masamitsu, Takeru Matsuoka, Takao Kamoshima