Patents by Inventor Takeshi Aoki

Takeshi Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240006424
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Application
    Filed: August 10, 2023
    Publication date: January 4, 2024
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA
  • Patent number: 11817780
    Abstract: A power supply circuit with a novel structure is provided.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: November 14, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Takeshi Aoki
  • Publication number: 20230363174
    Abstract: A ferroelectric device including a metal oxide film having favorable ferroelectricity is provided. The ferroelectric device includes a first conductor, a metal oxide film over the first conductor, and a second conductor over the metal oxide film. The metal oxide film has ferroelectricity. The metal oxide film has a crystal structure. The crystal structure includes a first layer and a second layer. The first layer contains first oxygen and hafnium. The second layer contains second oxygen and zirconium. The hafnium and the zirconium are bonded to each other through the first oxygen. The second oxygen is bonded to the zirconium.
    Type: Application
    Filed: September 9, 2021
    Publication date: November 9, 2023
    Inventors: Shunpei YAMAZAKI, Yasuhiro JINBO, Hitoshi KUNITAKE, Kazuaki OHSHIMA, Masashi OOTA, Kazuma FURUTANI, Takeshi AOKI
  • Publication number: 20230352502
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 2, 2023
    Inventors: Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA, Munehiro KOZUMA, Masataka IKEDA, Takeshi AOKI
  • Publication number: 20230352477
    Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a digital calculator, an analog calculator, a first memory circuit, and a second memory circuit. The analog calculator, the first memory circuit, and the second memory circuit each include a transistor including an oxide semiconductor in a channel formation region. The first memory circuit has a function of supplying first weight data to the digital calculator as digital data. The digital calculator has a function of performing product-sum operation using the first weight data. The second memory circuit has a function of supplying second weight data to the analog calculator as analog data. The analog calculator has a function of performing product-sum operation using the second weight data.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 2, 2023
    Inventors: Takanori MATSUZAKI, Tatsuya ONUKI, Munehiro KOZUMA, Takeshi AOKI, Yuki OKAMOTO, Takayuki IKEDA
  • Patent number: 11799430
    Abstract: A novel comparison circuit, a novel amplifier circuit, a novel battery control circuit, a novel battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. In a semiconductor device, one of a source and a drain of a first transistor is electrically connected to one of a source and a drain of a second transistor and one of a source and a drain of a third transistor; the other of the source and the drain of the third transistor is electrically connected to a first output terminal; and the other of the source and the drain of the second transistor is electrically connected to a second output terminal.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: October 24, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Takeshi Aoki, Munehiro Kozuma, Takayuki Ikeda
  • Publication number: 20230326491
    Abstract: A semiconductor device with a small circuit area and low power consumption is provided. The semiconductor device includes first to fourth cells, a current mirror circuit, and first to fourth wirings, and the first to fourth cells each include a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wiring is electrically connected to first terminals of the second transistors in the first cell and the second cell, the second wiring is electrically connected to first terminals of the second transistors in the third cell and the fourth cell, the third wiring is electrically connected to second terminals of the capacitors in the first cell and the third cell, and the fourth wiring is electrically connected to second terminals of the capacitors in the second cell and the fourth cell.
    Type: Application
    Filed: May 6, 2021
    Publication date: October 12, 2023
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Munehiro KOZUMA, Takuro KANEMURA, Tatsunori INOUE
  • Publication number: 20230326955
    Abstract: A semiconductor device with a small variation in characteristics is provided. In a manufacturing method of a semiconductor device including a capacitor with reduced leak current, a first conductor is formed; a second insulator is formed over the first conductor; a third insulator is formed over the second insulator; a second conductor is formed over the third insulator; a fourth insulator is deposited over the second conductor and the third insulator; by heat treatment, hydrogen contained in the third insulator diffuses into or is absorbed by the second insulator; the first conductor is one electrode of the capacitor; the second conductor is the other electrode of the capacitor; and each of the second insulator and the third insulator is a dielectric of the capacitor.
    Type: Application
    Filed: August 12, 2021
    Publication date: October 12, 2023
    Inventors: Shunpei YAMAZAKI, Sachiaki TEZUKA, Haruyuki BABA, Yuji EGI, Yasuhiro JINBO, Yujiro SAKURADA, Takeshi AOKI
  • Patent number: 11777502
    Abstract: A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: October 3, 2023
    Inventors: Hiroki Inoue, Munehiro Kozuma, Takeshi Aoki, Shuji Fukai, Fumika Akasawa, Sho Nagao
  • Patent number: 11755286
    Abstract: A semiconductor device capable of performing product-sum operation is provided. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. The semiconductor device retains first analog data and reference analog data in the first memory cell and the second memory cell, respectively. A potential corresponding to second analog data is applied to each of them as a selection signal, whereby current depending on the sum of products of the first analog data and the second analog data is obtained. The offset circuit includes a constant current circuit comprising a transistor and a capacitor. A first terminal of the transistor is electrically connected to a first gate of the transistor and a first terminal of the capacitor. A second gate of the transistor is electrically connected to a second terminal of the capacitor.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: September 12, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shintaro Harada, Yoshiyuki Kurokawa, Takeshi Aoki
  • Publication number: 20230278355
    Abstract: A head lifting lowering device includes: a lifting lowering mechanism that moves a liquid ejecting head, which ejects a liquid, in a first direction in which the liquid ejecting head is lifted/lowered; a frame that supports the lifting lowering mechanism; and an adjusting member that moves the lifting lowering mechanism relative to the frame in a second direction different from the first direction.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 7, 2023
    Inventors: Takeshi AOKI, Yusaku AMANO
  • Patent number: 11728354
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: August 15, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura
  • Patent number: 11710751
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: July 25, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura, Munehiro Kozuma, Masataka Ikeda, Takeshi Aoki
  • Publication number: 20230211619
    Abstract: A recording apparatus includes a recording unit including a recorder configured to perform recording on a medium, and a first side plate and a second side plate being a pair of side plates positioned across the recording unit, and configured to support the recording unit. An apparatus gravity center position is on a side close to the second side plate with respect to an intermediate position between the first side plate and the second side plate, and the number of components, of the recording unit, supported by the first side plate is smaller than the number of components, of the recording unit, supported by the second side plate.
    Type: Application
    Filed: October 28, 2022
    Publication date: July 6, 2023
    Inventors: Yusaku AMANO, Takeshi AOKI
  • Publication number: 20230200051
    Abstract: A semiconductor memory device comprises a memory cell array. The memory cell array comprises sub arrays. The sub array comprises: memory portions; first semiconductor layers electrically connected to memory portions; first gate electrodes respectively facing first semiconductor layers; a first wiring electrically connected to first semiconductor layers; second wirings connected to first gate electrodes; second semiconductor layers electrically connected to first end portions of second wirings; second gate electrodes facing second semiconductor layers; and a third wiring electrically connected to second semiconductor layers. The memory cell array comprises fourth wirings that extend in one direction across the sub arrays and are connected to second gate electrodes.
    Type: Application
    Filed: June 15, 2022
    Publication date: June 22, 2023
    Applicant: Kioxia Corporation
    Inventors: Takeshi AOKI, Masaharu WADA, Mamoru ISHIZAKA, Tsuneo INABA
  • Publication number: 20230174338
    Abstract: A printer, which is an example of a liquid ejecting apparatus, includes a movable body including a head for ejecting a liquid or a cap performing maintenance of the head. Further, the printer includes a pair of rack and pinion mechanisms including a rack and a drive gear to move the movable body in a first direction in which the rack extends; and a switching mechanism provided for each of the rack and pinion mechanisms and switching presence and absence of meshing between the rack and the drive gear when the movable body is at an exchange position.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 8, 2023
    Inventors: Yusaku AMANO, Takeshi AOKI
  • Publication number: 20230132059
    Abstract: A semiconductor device capable of performing product-sum operation with high layout flexibility is provided. In the semiconductor device, a first layer, a second layer, and a third layer are formed in this order. The first layer includes a first cell, a first circuit, a first wiring, and a second wiring adjacent to the first wiring. The second layer includes a third wiring and a fourth wiring adjacent to the third wiring. The third layer includes an electrode and a sensor. The first circuit includes a switch. The sensor is electrically connected to the third wiring through the electrode and a first plug, a first terminal of the switch is electrically connected to the third wiring through a second plug, and a second terminal of the switch is electrically connected to the first cell through the first wiring. The electrode includes a region overlapping with the sensor and a region overlapping with the first plug.
    Type: Application
    Filed: April 5, 2021
    Publication date: April 27, 2023
    Inventors: Yoshiyuki KUROKAWA, Munehiro KOZUMA, Takeshi AOKI, Takuro KANEMURA
  • Publication number: 20230114864
    Abstract: A power supply shutoff device includes a movable section, a driving section, a power supply device, a power distribution section, an electric power supply circuit, and a supply control section. The movable section is configured to travel on a traveling path provided along a board production line in which multiple board work machines, which perform a predetermined board work on a board, are installed side by side. The driving section is provided in the movable section and configured to cause the movable section to travel by using supply electric power supplied from the board work machine with non-contact power feeding. The supply control section is configured to stop a supply of the electric power to the electric power supply circuit when drive electric power for driving the board work machine is shut off in at least one board work machine among the multiple board work machines.
    Type: Application
    Filed: February 27, 2020
    Publication date: April 13, 2023
    Applicant: FUJI CORPORATION
    Inventors: Shingo FUJIMURA, Sota MIZUNO, Yusuke SAITO, Takeshi AOKI, Masato YAMAGIWA, Takashi HIRANO, Shigenori TANAKAMARU
  • Patent number: 11610544
    Abstract: An electronic device capable of efficiently recognizing a handwritten character is provided. The electronic device includes a first circuit, a display portion, and a touch sensor. The first circuit includes a neural network. The display portion includes a flexible display. The touch sensor has the function of outputting an input handwritten character as image information to the first circuit. The first circuit has the function of analyzing the image information and converting the image information into character information, and a function of displaying an image including the character information on the display portion. The analysis is performed by inference through the use of the neural network.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: March 21, 2023
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shintaro Harada, Yoshiyuki Kurokawa, Takeshi Aoki, Yuki Okamoto, Hiroki Inoue, Koji Kusunoki, Yosuke Tsukamoto, Katsuki Yanagawa, Kei Takahashi, Shunpei Yamazaki
  • Publication number: 20230082313
    Abstract: A semiconductor device with reduced power consumption that can perform a product-sum operation is provided. The semiconductor device includes first and second circuits, and the second circuit includes first and second switches, a current/voltage converter circuit, and a first transistor. The first circuit is electrically connected to a first terminal of the second circuit; a first terminal of the first switch is electrically connected to the first terminal of the second circuit; a second terminal of the first switch is electrically connected to an input terminal of the current/voltage converter circuit; an output terminal of the current/voltage converter circuit is electrically connected to a first terminal of the first transistor; a second terminal of the first transistor is electrically connected to a first terminal of the second switch; and a second terminal of the second switch is electrically connected to a second terminal of the second circuit.
    Type: Application
    Filed: February 12, 2021
    Publication date: March 16, 2023
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Munehiro KOZUMA, Takuro KANEMURA