Patents by Inventor Takeshi Hamamoto

Takeshi Hamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10894471
    Abstract: A mounting structure for a power conversion device includes: a vehicle body component extending in a front-rear direction of a vehicle; a mounting component provided on the vehicle body component; a drive unit held by the vehicle body component via the mounting component; and a power conversion device attached to the mounting component. A stiffness of the mounting component is greater than a stiffness of the vehicle body component. The power conversion device is arranged between a front end and a rear end of the drive unit in a side view of the vehicle.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: January 19, 2021
    Assignee: NISSAN MOTOR CO., LTD.
    Inventors: Nobuaki Yokoyama, Mikio Nozaki, Hiroki Wada, Takahiro Kurosawa, Takeshi Hamamoto, Anna Hayashi, Tomoya Kamada, Takashi Yoshikawa
  • Patent number: 10706177
    Abstract: A semiconductor device including a semiconductor chip having a cell array is provided. The cell array includes identification cells distributed in sub-blocks of the cell array. The identification cell has a cell address and the sub-block has a block address. The cell address is related to the block address. A portion of the block addresses include the cell address at which an identification cell exhibiting a predetermined characteristic is located. The predetermined characteristic is based on a physical randomness which is intrinsic of the semiconductor chip. The semiconductor chip further has a physical random number code including the portion of the block address. The physical random number code is secured by the semiconductor chip. This disclosure provides the technology to prevent malicious manipulation of physical addresses by artfully incorporating physical network with logical network, and to make the administration of hardware network more secure.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: July 7, 2020
    Inventors: Hiroshi Watanabe, Takeshi Hamamoto
  • Publication number: 20200173523
    Abstract: The present invention relates to a V-ribbed belt in which a frictional power-transmission surface is formed from a weft knitted multilayer knitted fabric, characterized in that the weft knitted multilayer knitted fabric contains cellulose based natural spun yarn, polyester based composite yarn, and polyamide based yarn, and in that at least the cellulose based natural spun yarn and the polyamide based yarn are disposed in a layer on the frictional power-transmission surface side.
    Type: Application
    Filed: May 23, 2018
    Publication date: June 4, 2020
    Applicant: Mitsuboshi Belting Ltd.
    Inventors: Kouhei Hamamoto, Takeshi Nishiyama
  • Publication number: 20200135261
    Abstract: According to a control device of a first aspect of the invention, for a semiconductor memory device comprising an interface conforming to JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM, the control device comprises a plurality of banks, a read/write control circuit, and a transfer control circuit. The banks are connected to one another by an internal data bus, and each bank, separated from one another by at least one sense amplifier row comprising a plurality of sense amplifiers, comprises a plurality of subarrays. Each subarray comprises a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to the bit lines. The read/write control circuit controls reading of data from the semiconductor memory device and writing of data to the semiconductor memory device.
    Type: Application
    Filed: March 6, 2017
    Publication date: April 30, 2020
    Inventors: Masaru Haraguchi, Takashi Kubo, Yasuhiko Tsukikawa, Hironori Iga, Kenichi Yasuda, Takeshi Hamamoto
  • Patent number: 10581841
    Abstract: An authenticated network in which a physical network including physical nodes with actual physical substances and a logical network including logical nodes without actual substances are uniquely linked to expand public ledger technology, which secures Peer-to-peer (P2P) type communication on a logical network, to a physical network, is provided. The authenticated network includes a private key uniquely linked to a public key. The private key is generated by a key generator and an identification device having physical substance and included in an identification core. The private key is regarded as a physical address of the identification core and is confined in the identification core. The public key is publicized as a logical address of a logical node. The logical node and the physical node are uniquely linked by the public key and the private key. The security of the whole network is thus effectively improved.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: March 3, 2020
    Assignee: Zentel Japan Corporation
    Inventors: Hiroshi Watanabe, Takeshi Hamamoto
  • Publication number: 20190378561
    Abstract: A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.
    Type: Application
    Filed: January 31, 2017
    Publication date: December 12, 2019
    Inventors: TAKASHI KUBO, MASARU HARAGUCHI, TAKESHI HAMAMOTO, KENICHI YASUDA, YASUHIKO TSUKIKAWA, HIRONORI IGA
  • Publication number: 20190337374
    Abstract: A mounting structure for a power conversion device includes: a vehicle body component extending in a front-rear direction of a vehicle; a mounting component provided on the vehicle body component; a drive unit held by the vehicle body component via the mounting component; and a power conversion device attached to the mounting component. A stiffness of the mounting component is greater than a stiffness of the vehicle body component. The power conversion device is arranged between a front end and a rear end of the drive unit in a side view of the vehicle.
    Type: Application
    Filed: May 25, 2016
    Publication date: November 7, 2019
    Applicant: NISSAN MOTOR CO., LTD.
    Inventors: Nobuaki YOKOYAMA, Mikio NOZAKI, Hiroki WADA, Takahiro KUROSAWA, Takeshi HAMAMOTO, Anna HAYASHI, Tomoya KAMADA, Takashi YOSHIKAWA
  • Publication number: 20190264923
    Abstract: A combustor liner used for a gas turbine combustor and forming a combustion chamber includes: an outer side wall made of metal; a panel attached to an inner side of the outer side wall and made of a ceramic matrix composite material, the panel including a panel body facing the combustion chamber, and a connection piece rising from an exterior surface of the panel body at a side portion of the panel body and protruding in a lateral direction; and a connection unit configured to connect the panel to the outer side wall, the connection unit including an elastic member configured to bias at least one of the outer side wall and the connection piece, and a fixation member made of metal and configured to fix at least one of the connection piece and the elastic member to the outer side wall.
    Type: Application
    Filed: May 9, 2019
    Publication date: August 29, 2019
    Applicant: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Masayoshi KOBAYASHI, Takeo ODA, Takeo NISHIURA, Tomoko TSURU, Takaya HAMAMOTO, Takeshi TAKAGI, Osamu HISAMATSU, Hirotaka KURASHIMA
  • Publication number: 20180232539
    Abstract: A semiconductor device including a semiconductor chip having a cell array is provided. The cell array includes identification cells distributed in sub-blocks of the cell array. The identification cell has a cell address and the sub-block has a block address. The cell address is related to the block address. A portion of the block addresses include the cell address at which an identification cell exhibiting a predetermined characteristic is located. The predetermined characteristic is based on a physical randomness which is intrinsic of the semiconductor chip. The semiconductor chip further has a physical random number code including the portion of the block address. The physical random number code is secured by the semiconductor chip. This disclosure provides the technology to prevent malicious manipulation of physical addresses by artfully incorporating physical network with logical network, and to make the administration of hardware network more secure.
    Type: Application
    Filed: June 30, 2017
    Publication date: August 16, 2018
    Inventors: Hiroshi Watanabe, TAKESHI HAMAMOTO
  • Publication number: 20180234413
    Abstract: An authenticated network in which a physical network including physical nodes with actual physical substances and a logical network including logical nodes without actual substances are uniquely linked to expand public ledger technology, which secures P2P type communication on logical network, to physical network, is provided. The authenticated network includes a private key uniquely linked to a public key. The private key is generated by a key generator and an identification device having physical substance and included in an identification core. The private key is regarded as physical address of the identification core and is confined in the identification core. The public key is publicized as a logical address of a logical node. The logical node and the physical node are uniquely linked by the public key and the private key. The security of the whole network is thus effectively improved.
    Type: Application
    Filed: February 13, 2017
    Publication date: August 16, 2018
    Inventors: Hiroshi Watanabe, Takeshi Hamamoto
  • Patent number: 10049711
    Abstract: According to one embodiment, a magnetoresistive memory device includes a substrate having a first surface which includes a first direction; and memory elements each having a switchable resistance. A first column of memory elements lined up along the first direction is different from an adjacent second column of memory elements lined up along the first direction at positions of memory elements in the first direction.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: August 14, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keisuke Nakatsuka, Tadashi Miyakawa, Katsuhiko Hoya, Takeshi Hamamoto, Hiroyuki Takenaka
  • Publication number: 20160379701
    Abstract: According to one embodiment, a magnetoresistive memory device includes a substrate having a first surface which includes a first direction; and memory elements each having a switchable resistance. A first column of memory elements lined up along the first direction is different from an adjacent second column of memory elements lined up along the first direction at positions of memory elements in the first direction.
    Type: Application
    Filed: September 6, 2016
    Publication date: December 29, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keisuke NAKATSUKA, Tadashi MIYAKAWA, Katsuhiko HOYA, Takeshi HAMAMOTO, Hiroyuki TAKENAKA
  • Patent number: 9406720
    Abstract: A memory includes first to fifth WLs extending in a first-direction. First to fourth element-regions extend in a tilt-direction. The first to fourth element-regions, respectively, intersect with the first and second WLs, with the third and fourth WLs, with the second and third WLs, and with the fourth and fifth WLs. A first connection-portion is arranged on an end of the first element-region and an end of the second element-region between the second and third WLs. A second connection-portion is arranged on an end of the third element-region and an end of the fourth element-region between the third and fourth WLs. First to fourth MTJs are, respectively, arranged above the first to fourth element-regions. The first and second MTJs are on a substantially same line along a second direction orthogonal to the first direction. The third and fourth MTJs are on a substantially same line along the second direction.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: August 2, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Hamamoto
  • Publication number: 20160043134
    Abstract: A memory includes first to fifth WLs extending in a first-direction. First to fourth element-regions extend in a tilt-direction. The first to fourth element-regions, respectively, intersect with the first and second WLs, with the third and fourth WLs, with the second and third WLs, and with the fourth and fifth WLs. A first connection-portion is arranged on an end of the first element-region and an end of the second element-region between the second and third WLs. A second connection-portion is arranged on an end of the third element-region and an end of the fourth element-region between the third and fourth WLs. First to fourth MTJs are, respectively, arranged above the first to fourth element-regions. The first and second MTJs are on a substantially same line along a second direction orthogonal to the first direction. The third and fourth MTJs are on a substantially same line along the second direction.
    Type: Application
    Filed: March 11, 2015
    Publication date: February 11, 2016
    Inventor: Takeshi HAMAMOTO
  • Patent number: 8643105
    Abstract: This disclosure concerns a semiconductor memory device including a semiconductor substrate; a buried insulation film provided on the semiconductor substrate; a semiconductor layer provided on the buried insulation film; a source layer and a drain layer provided in the semiconductor layer; a body region provided in the semiconductor layer between the source layer and the drain layer, and being in an electrically floating state, the body region accumulating or discharging charges to store data; a gate dielectric film provided on the body region; a gate electrode provided on the gate dielectric film; and a plate electrode facing a side surface of the body region via an insulation film, in an element isolation region.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: February 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Hamamoto
  • Patent number: 8482044
    Abstract: An aspect of the present disclosure, there is provided semiconductor memory device including a ferroelectric capacitor and a field effect transistor as a memory cell, the ferroelectric capacitor including a lower electrode connected to one of the pair of the impurity diffusion layers, a bit line formed below the lower electrode, wherein each of the memory cells shares the bit line contact with an adjacent memory cell at one side in the first direction to connect to the bit line, and three of the word lines are formed between the bit line contacts in the first direction.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: July 9, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Hamamoto
  • Patent number: 7995369
    Abstract: This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: August 9, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Minami, Ryo Fukuda, Takeshi Hamamoto
  • Patent number: 7977738
    Abstract: A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: July 12, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Minami, Takashi Ohsawa, Tomoaki Shino, Takeshi Hamamoto, Akihiro Nitayama
  • Patent number: 7952162
    Abstract: A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: May 31, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Hamamoto
  • Publication number: 20110062504
    Abstract: An aspect of the present disclosure, there is provided semiconductor memory device including a ferroelectric capacitor and a field effect transistor as a memory cell, the ferroelectric capacitor including a lower electrode connected to one of the pair of the impurity diffusion layers, a bit line formed below the lower electrode, wherein each of the memory cells shares the bit line contact with an adjacent memory cell at one side in the first direction to connect to the bit line, and three of the word lines are formed between the bit line contacts in the first direction.
    Type: Application
    Filed: March 10, 2010
    Publication date: March 17, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takeshi HAMAMOTO