Patents by Inventor Takeshi Ishizaki
Takeshi Ishizaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9570464Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a first metal nitride film on a side surface of a hole extending in a stacking direction in a stacked body. The method includes forming a second metal nitride film on upper and lower surfaces of second layers and a side surface of the first metal nitride film. The method includes forming metal layers in first air gaps inside the second metal nitride film. The method includes removing the second layers and forming second air gaps between the metal layers. The method includes removing the first metal nitride film exposed to the second air gaps and dividing the first metal nitride film in the stacking direction.Type: GrantFiled: March 18, 2016Date of Patent: February 14, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Wakatsuki, Atsuko Sakata, Masayuki Kitamura, Daisuke Ikeno, Takeshi Ishizaki, Tomotaka Ariga
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Publication number: 20160300845Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a film having semi-conductivity or conductivity, and a memory film. The stacked body includes a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers stacked on a major surface of the substrate. The film extends in the stacked body in a stacking direction of the stacked body. The memory film is provided between the film and the metal layers. The metal layers are tungsten layers and the intermediate layers are tungsten nitride layers. Or the metal layers are molybdenum layers and the intermediate layers are molybdenum nitride layers.Type: ApplicationFiled: August 18, 2015Publication date: October 13, 2016Inventors: Takeshi ISHIZAKI, Junichi WADA, Atsuko SAKATA, Kei WATANABE, Masayuki KITAMURA, Daisuke IKENO, Satoshi WAKATSUKl, Hirotaka OGIHARA, Shinya OKUDA
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Publication number: 20160276204Abstract: A method of manufacturing a semiconductor device uses a semiconductor manufacturing apparatus including a turn table allowing placement of at least first and second semiconductor substrates and being capable of moving positions of the first and the second semiconductor substrates by turning, a first film forming chamber, and a second film forming chamber. The first and the second film forming chambers are provided with an opening capable of loading and unloading the first and the second semiconductor substrates by lifting and lowering the first and the second semiconductor substrates placed on the turn table. The method includes transferring the first and the second semiconductor substrates between the first and the second film forming chambers by turning the turn fable and lifting and lowering the first and the second semiconductor substrates placed on the turn table; and forming a stack of films above the first and the second semiconductor substrates.Type: ApplicationFiled: June 26, 2015Publication date: September 22, 2016Inventors: Atsuko SAKATA, Kei Watanabe, Junichi Wada, Masayuki Kitamura, Takeshi Ishizaki, Shinya Okuda, Hirotaka Ogihara, Satoshi Wakatsuki, Daisuke Ikeno
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Publication number: 20160268283Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers; a first electrode layer included in the plurality of electrode layers; a second electrode layer included in the plurality of electrode layers; a first insulating layer provided between the first electrode layer and the second electrode layer, and provided in contact with the first electrode layer and the second electrode layer; a semiconductor portion; a charge storage film; a first conductive film; and second conductive film. The first conductive film is provided between the first electrode layer and the charge storage film, and provided in contact with the first insulating layer. The second conductive film is provided between the second electrode layer and the charge storage film, and provided in contact with the first insulating layer.Type: ApplicationFiled: July 9, 2015Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Masayuki KITAMURA, Atsuko Sakata, Satoshi Wakatsuki, Takeshi Ishizaki, Daisuke Ikeno, Junichi Wada, Kei Watanabe, Shinya Okuda, Hirotaka Ogihara, Hiroshi Nakazawa, Tomonori Aoyama, Kenji Aoyama, Hideaki Aochi
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Publication number: 20160268275Abstract: A non-volatile memory device includes a first semiconductor body extending in a first direction, an electrode extending in a second direction intersecting the first direction, a charge storage layer provided between the first semiconductor body and the electrode, and a first insulating layer provided between the electrode and the charge storage layer. The electrode includes a first layer, a second layer and a third layer. The first layer is provided on the first insulating layer and includes tungsten. The second layer is provided on the first layer and includes tungsten nitride. The third layer is provided on the second layer and includes tungsten.Type: ApplicationFiled: August 27, 2015Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Yuta WATANABE, Takeshi ISHIZAKI, Kana HIRAYAMA, Kenji AOYAMA
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Patent number: 9412683Abstract: According to one embodiment, a semiconductor device having an interlayer insulating film, a molybdenum containing layer, a barrier metal layer and a plug material layer is provided. The interlayer insulating film is formed on a substrate or on a conductive layer formed on a substrate. The interlayer insulating film has a hole reaching the substrate or the conductive layer. The molybdenum containing layer is formed in the substrate or in the conductive layer at a bottom portion of the hole. The barrier metal layer is formed on the molybdenum containing layer and on a side surface of the hole. A portion of the barrier metal layer is formed on the side surface contains at least molybdenum. A portion of the barrier metal layer is formed on the molybdenum containing layer includes at least a molybdenum silicate nitride film. The plug material layer is formed via the barrier metal layer.Type: GrantFiled: April 2, 2015Date of Patent: August 9, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Sakata, Takeshi Ishizaki
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Publication number: 20160064405Abstract: According to one embodiment, forming a metal film on an underlying layer, and depositing an oxide film on the metal film using plasma of a mixed gas induced above the metal film. The mixed gas includes a gaseous material source, a gaseous oxidant, and a gaseous reductant.Type: ApplicationFiled: January 30, 2015Publication date: March 3, 2016Inventors: SHINYA OKUDA, KEI WATANABE, HIROTAKA OGIHARA, MASAYUKI KITAMURA, TAKESHI ISHIZAKI, DAISUKE IKENO, SATOSHI WAKATSUKI, ATSUKO SAKATA, JUNICHI WADA
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Publication number: 20150206828Abstract: According to one embodiment, a semiconductor device having an interlayer insulating film, a molybdenum containing layer, a barrier metal layer and a plug material layer is provided. The interlayer insulating film is formed on a substrate or on a conductive layer formed on a substrate. The interlayer insulating film has a hole reaching the substrate or the conductive layer. The molybdenum containing layer is formed in the substrate or in the conductive layer at a bottom portion of the hole. The barrier metal layer is formed on the molybdenum containing layer and on a side surface of the hole. A portion of the barrier metal layer is formed on the side surface contains at least molybdenum. A portion of the barrier metal layer is formed on the molybdenum containing layer includes at least a molybdenum silicate nitride film. The plug material layer is formed via the barrier metal layer.Type: ApplicationFiled: April 2, 2015Publication date: July 23, 2015Inventors: Atsuko Sakata, Takeshi Ishizaki
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Patent number: 9018764Abstract: According to one embodiment, a semiconductor device having an interlayer insulating film, a molybdenum containing layer, a barrier metal layer and a plug material layer is provided. The interlayer insulating film is formed on a substrate or on a conductive layer formed on a substrate. The interlayer insulating film has a hole reaching the substrate or the conductive layer. The molybdenum containing layer is formed in the substrate or in the conductive layer at a bottom portion of the hole. The barrier metal layer is formed on the molybdenum containing layer and on a side surface of the hole. A portion of the barrier metal layer is formed on the side surface contains at least molybdenum. A portion of the barrier metal layer is formed on the molybdenum containing layer includes at least a molybdenum silicate nitride film. The plug material layer is formed via the barrier metal layer.Type: GrantFiled: September 5, 2013Date of Patent: April 28, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Sakata, Takeshi Ishizaki
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Patent number: 8922018Abstract: According to one embodiment, a semiconductor device includes an interconnect provided on a first interlayer insulating film covering a semiconductor substrate in which an element is formed, a cap layer provided on the upper surface of the interconnect, and a barrier film provided between the interconnect and a second interlayer insulating film covering the interconnect. The interconnect includes a high-melting-point conductive layer, and the width of the interconnect is smaller than the width of the cap layer. The barrier film includes a compound of a contained element in the high-melting-point conductive layer.Type: GrantFiled: March 22, 2012Date of Patent: December 30, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Ishizaki, Atsuko Sakata, Junichi Wada, Masahiko Hasunuma
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Patent number: 8907484Abstract: According to an embodiment, a semiconductor device, includes a substrate, an inter-layer insulating layer provided above the substrate, a first interconnect provided in a first trench, and a second interconnect provided in a second trench. The first interconnect is made of a first metal, and the first trench is provided in the inter-layer insulating layer on a side opposite to the substrate. The second interconnect is made of a second metal, and the second trench is provided in the inter-layer insulating layer toward the substrate. A width of the second trench is wider than a width of the first trench. A mean free path of electrons in the first metal is shorter than a mean free path of electrons in the second metal, and the first metal is a metal, an alloy or a metal compound, including at least one nonmagnetic element as a constituent element.Type: GrantFiled: September 5, 2013Date of Patent: December 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Kitamura, Atsuko Sakata, Takeshi Ishizaki, Satoshi Wakatsuki
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Publication number: 20140284801Abstract: According to an embodiment, a semiconductor device, includes a substrate, an inter-layer insulating layer provided above the substrate, a first interconnect provided in a first trench, and a second interconnect provided in a second trench. The first interconnect is made of a first metal, and the first trench is provided in the inter-layer insulating layer on a side opposite to the substrate. The second interconnect is made of a second metal, and the second trench is provided in the inter-layer insulating layer toward the substrate. A width of the second trench is wider than a width of the first trench. A mean free path of electrons in the first metal is shorter than a mean free path of electrons in the second metal, and the first metal is a metal, an alloy or a metal compound, including at least one nonmagnetic element as a constituent element.Type: ApplicationFiled: September 5, 2013Publication date: September 25, 2014Inventors: Masayuki KITAMURA, Atsuko SAKATA, Takeshi ISHIZAKI, Satoshi WAKATSUKI
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Publication number: 20140070417Abstract: According to one embodiment, a semiconductor device having an interlayer insulating film, a molybdenum containing layer, a barrier metal layer and a plug material layer is provided. The interlayer insulating film is formed on a substrate or on a conductive layer formed on a substrate. The interlayer insulating film has a hole reaching the substrate or the conductive layer. The molybdenum containing layer is formed in the substrate or in the conductive layer at a bottom portion of the hole. The barrier metal layer is formed on the molybdenum containing layer and on a side surface of the hole. A portion of the barrier metal layer is formed on the side surface contains at least molybdenum. A portion of the barrier metal layer is formed on the molybdenum containing layer includes at least a molybdenum silicate nitride film. The plug material layer is formed via the barrier metal layer.Type: ApplicationFiled: September 5, 2013Publication date: March 13, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsuko SAKATA, Takeshi ISHIZAKI
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Patent number: 8637380Abstract: According to one embodiment, a method of manufacturing a semiconductor device including forming a metal film on aback surface of a glass substrate which supports a semiconductor substrate on a front surface thereof; forming a metal oxide film by oxidizing the whole or at least a portion of the metal film from the front surface; forming protective film, such as silicon nitride, on the metal oxide film; holding the front surface of the protective film with an electrostatic chuck; and forming a via for electrical connection in the semiconductor substrate while the front surface of the protective film is in contact with by the electrostatic chuck; then using a laser to delaminate the glass substrate from the semiconductor substrate.Type: GrantFiled: September 7, 2012Date of Patent: January 28, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Sakata, Kazuyuki Higashi, Akiko Nomachi, Takeshi Ishizaki
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Publication number: 20130252421Abstract: According to one embodiment, a method of manufacturing a semiconductor device including forming a metal film on aback surface of a glass substrate which supports a semiconductor substrate on a front surface thereof; forming a metal oxide film by oxidizing the whole or at least a portion of the metal film from the front surface; forming protective film, such as silicon nitride, on the metal oxide film; holding the front surface of the protective film with an electrostatic chuck; and forming a via for electrical connection in the semiconductor substrate while the front surface of the protective film is in contact with by the electrostatic chuck; then using a laser to delaminate the glass substrate from the semiconductor substrate.Type: ApplicationFiled: September 7, 2012Publication date: September 26, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsuko Sakata, Kazuyuki Higashi, Akiko Nomachi, Takeshi Ishizaki
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Publication number: 20120306081Abstract: According to one embodiment, a semiconductor device includes an interconnect provided on a first interlayer insulating film covering a semiconductor substrate in which an element is formed, a cap layer provided on the upper surface of the interconnect, and a barrier film provided between the interconnect and a second interlayer insulating film covering the interconnect. The interconnect includes a high-melting-point conductive layer, and the width of the interconnect is smaller than the width of the cap layer. The barrier film includes a compound of a contained element in the high-melting-point conductive layer.Type: ApplicationFiled: March 22, 2012Publication date: December 6, 2012Inventors: Takeshi ISHIZAKI, Atsuko Sakata, Junichi Wada, Masahiko Hasunuma
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Patent number: 8151079Abstract: Disclosed is a system and method for preventing deterioration in I/O performance of a computer resulted from a use of the same physical disk among different logical volumes. A volume management server 1010 groups together logical volumes which use the same physical disk of a storage device 1020 as a volume group and allocates a storage area on the physical disk to be used on a priority basis by this volume group to the volume group, and thereby a physical arrangement according to a present physical arrangement of the logical volume can be performed when an automatic expansion of the logical volume is performed thereafter so that the I/O performance deterioration of the computer caused by a mutual interference is avoided at the time of access from the computer 1030 to the storage device 1020.Type: GrantFiled: September 14, 2011Date of Patent: April 3, 2012Assignee: Hitatchi, Ltd.Inventors: Jun Mizuno, Takeshi Ishizaki
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Publication number: 20120005428Abstract: Disclosed is a system and method for preventing deterioration in I/O performance of a computer resulted from a use of the same physical disk among different logical volumes. A volume management server 1010 groups together logical volumes which use the same physical disk of a storage device 1020 as a volume group and allocates a storage area on the physical disk to be used on a priority basis by this volume group to the volume group, and thereby a physical arrangement according to a present physical arrangement of the logical volume can be performed when an automatic expansion of the logical volume is performed thereafter so that the I/O performance deterioration of the computer caused by a mutual interference is avoided at the time of access from the computer 1030 to the storage device 1020.Type: ApplicationFiled: September 14, 2011Publication date: January 5, 2012Inventors: JUN MIZUNO, Takeshi Ishizaki
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Patent number: 8037276Abstract: Disclosed is a system and method for preventing deterioration in I/O performance of a computer resulted from a use of the same physical disk among different logical volumes. A volume management server 1010 groups together logical volumes which use the same physical disk of a storage device 1020 as a volume group and allocates a storage area on the physical disk to be used on a priority basis by this volume group to the volume group, and thereby a physical arrangement according to a present physical arrangement of the logical volume can be performed when an automatic expansion of the logical volume is performed thereafter so that the I/O performance deterioration of the computer caused by a mutual interference is avoided at the time of access from the computer 1030 to the storage device 1020.Type: GrantFiled: January 4, 2010Date of Patent: October 11, 2011Assignee: Hitachi, Ltd.Inventors: Jun Mizuno, Takeshi Ishizaki
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Patent number: 7962601Abstract: The present invention provides techniques for creation, operation, management, and access control of network-based storage services. Specific embodiments provide improved efficiency of the service management tasks used for designing, operating and accounting the robust and profitable network services, for example. In representative embodiments, techniques for constructing integrated network and storage services are provided. In a specific embodiment, the service comprises of three major service components: virtual private networks (VPN), application servers and storage area networks (SAN). Each of these service components has its own customer identification information, such as VPN identifier for VPN services, process identifier for application servers and logical unit number (LUN) for storage devices.Type: GrantFiled: February 12, 2010Date of Patent: June 14, 2011Assignee: Hitachi, Ltd.Inventors: Takeshi Ishizaki, Shigeru Miyake