Patents by Inventor Takeshi Kajiyama

Takeshi Kajiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9263666
    Abstract: A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: February 16, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi Kajiyama, Yoshiaki Asao
  • Patent number: 9190453
    Abstract: According to one embodiment, a magnetic memory including an isolation region with an insulator in a trench is disclosed. The isolation region defines active areas extending in a 1st direction and having 1st and 2nd active areas, an isolation region extending in a 2nd direction perpendicular to the 1st direction exists between the 1st and 2nd active areas. 1st and 2nd word lines extending in the 2nd direction are buried in a surface of semiconductor substrate. 1st and 2nd select transistors connected to the word lines are on the 1st active area. 1st and 2nd variable resistance elements connected to drain regions of the 1st and 2nd select transistors are on the 1st active area.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: November 17, 2015
    Inventors: Takashi Nakazawa, Yoshiaki Asao, Takeshi Kajiyama, Kenji Noma
  • Patent number: 9130034
    Abstract: According to an embodiment, semiconductor device includes a semiconductor substrate, first and second isolation regions provided in the semiconductor substrate, extending in a first direction, and adjacent to each other, first and second word lines provided in the semiconductor substrate, extending in a second direction crossing the first direction, and adjacent to each other, first and second upper insulating regions provided on the first and second word lines, extending in the second direction, and adjacent to each other, a source/drain diffusion region provided in a surface area of the semiconductor substrate and between the first and second isolation regions, and including a portion positioned between the first and second upper insulating regions, and a first conductive portion provided in the source/drain diffusion region and formed of a material containing metal.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: September 8, 2015
    Inventor: Takeshi Kajiyama
  • Publication number: 20150155332
    Abstract: According to one embodiment, a magnetic memory including an isolation region with an insulator in a trench is disclosed. The isolation region defines active areas extending in a 1st direction and having 1st and 2nd active areas, an isolation region extending in a 2nd direction perpendicular to the 1st direction exists between the 1st and 2nd active areas. 1st and 2nd word lines extending in the 2nd direction are buried in a surface of semiconductor substrate. 1st and 2nd select transistors connected to the word lines are on the 1st active area. 1st and 2nd variable resistance elements connected to drain regions of the 1st and 2nd select transistors are on the 1st active area.
    Type: Application
    Filed: February 13, 2015
    Publication date: June 4, 2015
    Inventors: Takashi NAKAZAWA, Yoshiaki ASAO, Takeshi KAJIYAMA, Kenji NOMA
  • Publication number: 20150137290
    Abstract: A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni.
    Type: Application
    Filed: December 8, 2014
    Publication date: May 21, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi KAJIYAMA, Yoshiaki Asao
  • Patent number: 9029943
    Abstract: The semiconductor memory device includes a cell transistor having a gate insulating film deposited on an inner surface of a groove formed in an upper surface of the semiconductor substrate, a gate electrode buried in the groove with the gate insulating film formed on the inner surface thereof, and a source region and a drain region formed on an upper surface of the active area of the semiconductor substrate on opposite sides of the gate electrode. The semiconductor memory device includes an MTJ element having a variable resistance that varies with a direction of magnetization that is provided on the source region and electrically connected to the source region at a first end thereof.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: May 12, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama
  • Patent number: 9000545
    Abstract: A magnetic random access memory includes a semiconductor substrate, an MTJ element formed from a perpendicular magnetization film and arranged above the semiconductor substrate, and a stress film including at least one of a tensile stress film arranged on an upper side of the MTJ element to apply a stress in a tensile direction with respect to the semiconductor substrate and a compressive stress film arranged on a lower side of the MTJ element to apply a stress in a compressive direction with respect to the semiconductor substrate.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama
  • Patent number: 8981446
    Abstract: According to one embodiment, a magnetic memory including an isolation region with an insulator in a trench is disclosed. The isolation region defines active areas extending in a 1st direction and having 1st and 2nd active areas, an isolation region extending in a 2nd direction perpendicular to the 1st direction exists between the 1st and 2nd active areas. 1st and 2nd word lines extending in the 2nd direction are buried in a surface of semiconductor substrate. 1st and 2nd select transistors connected to the word lines are on the 1st active area. 1st and 2nd variable resistance elements connected to drain regions of the 1st and 2nd select transistors are on the 1st active area.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: March 17, 2015
    Inventors: Takashi Nakazawa, Yoshiaki Asao, Takeshi Kajiyama, Kenji Noma
  • Publication number: 20150069479
    Abstract: According to an embodiment, semiconductor device includes a semiconductor substrate, first and second isolation regions provided in the semiconductor substrate, extending in a first direction, and adjacent to each other, first and second word lines provided in the semiconductor substrate, extending in a second direction crossing the first direction, and adjacent to each other, first and second upper insulating regions provided on the first and second word lines, extending in the second direction, and adjacent to each other, a source/drain diffusion region provided in a surface area of the semiconductor substrate and between the first and second isolation regions, and including a portion positioned between the first and second upper insulating regions, and a first conductive portion provided in the source/drain diffusion region and formed of a material containing metal.
    Type: Application
    Filed: December 9, 2013
    Publication date: March 12, 2015
    Inventor: Takeshi KAJIYAMA
  • Patent number: 8941197
    Abstract: A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: January 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kajiyama, Yoshiaki Asao
  • Publication number: 20140284738
    Abstract: According to one embodiment, a magnetic memory including an isolation region with an insulator in a trench is disclosed. The isolation region defines active areas extending in a 1st direction and having 1st and 2nd active areas, an isolation region extending in a 2nd direction perpendicular to the 1st direction exists between the 1st and 2nd active areas. 1st and 2nd word lines extending in the 2nd direction are buried in a surface of semiconductor substrate. 1st and 2nd select transistors connected to the word lines are on the 1st active area. 1st and 2nd variable resistance elements connected to drain regions of the 1st and 2nd select transistors are on the 1st active area.
    Type: Application
    Filed: September 4, 2013
    Publication date: September 25, 2014
    Inventors: Takashi NAKAZAWA, Yoshiaki ASAO, Takeshi KAJIYAMA, Kenji NOMA
  • Patent number: 8829580
    Abstract: According to one embodiment, a magnetoresistive memory includes first and second contact plugs in a first interlayer insulating film, a lower electrode on the first interlayer insulating film, a magnetoresistive effect element on the lower electrode, and an upper electrode on the magnetoresistive effect element. The lower electrode has a tapered cross-sectional shape in which a dimension of a bottom surface of the lower electrode is longer than a dimension of an upper surface of the lower electrode, one end of the lower electrode is in contact with an upper surface of the first contact plug. The magnetoresistive effect element is provided at a position shifted from a position immediately above the first contact plug in a direction parallel to a surface of the semiconductor substrate.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kuniaki Sugiura, Yoshiaki Asao, Takeshi Kajiyama
  • Publication number: 20140001525
    Abstract: The semiconductor memory device includes a cell transistor having a gate insulating film deposited on an inner surface of a groove formed in an upper surface of the semiconductor substrate, a gate electrode buried in the groove with the gate insulating film formed on the inner surface thereof, and a source region and a drain region formed on an upper surface of the active area of the semiconductor substrate on opposite sides of the gate electrode. The semiconductor memory device includes an MTJ element having a variable resistance that varies with a direction of magnetization that is provided on the source region and electrically connected to the source region at a first end thereof.
    Type: Application
    Filed: February 28, 2013
    Publication date: January 2, 2014
    Inventor: Takeshi KAJIYAMA
  • Patent number: 8607259
    Abstract: A disk laminate includes thin disks laminated to each other, which are to be suctioned and conveyed; and spacers provided between the thin disks to prevent the thin disks from directly contacting each other, the spacers having air permeability.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: December 10, 2013
    Assignees: Ricoh Company, Ltd., Chotaro Engineering, Co.
    Inventors: Yoshimichi Takano, Nobuaki Onagi, Kohji Tsukahara, Haruki Tokumaru, Daiichi Koide, Takeshi Kajiyama, Masami Nishida
  • Patent number: 8592928
    Abstract: According to one embodiment, a magnetic random access memory includes a selection element formed on a semiconductor substrate, an interlayer dielectric film formed above the selection element, a contact layer formed in the interlayer dielectric film, and electrically connected to the selection element, a lower electrode layer made of a metal material, and electrically connected to the contact layer, a metal oxide insulating film made of an oxide of the metal material, and surrounding a side surface of the lower electrode layer, a magnetoresistive element formed on the lower electrode layer, an upper electrode layer formed on the magnetoresistive element, a sidewall insulating film formed on a side surface of the magnetoresistive element and a side surface of the upper electrode layer, and a bit line electrically connected to the upper electrode layer.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: November 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Hiroyuki Kanaya, Takeshi Kajiyama
  • Patent number: 8587042
    Abstract: An aspect of the present disclosure, there is provided a magnetoresistive random access memory device, including, an active area formed on a semiconductor substrate in a first direction, a magnetoresistive effect element formed on the active area and storing data by a change in resistance value, a gate electrode of a cell transistor formed on each side of the magnetoresistive effect element on the active area in a second direction, a bit line contact formed on the active area and arranged alternately with the magnetoresistive effect element, a first bit line connected to the magnetoresistive effect, and a second bit line connected to the bit line contact.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: November 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama
  • Patent number: 8549547
    Abstract: A disclosed disk clamping mechanism includes a turntable fixed on a rotational shaft of a spindle motor to rotate a flexible thin optical disk, a stabilizer member configured to suppress a run-out of the flexible thin optical disk by an applying aerodynamic force to the rotating flexible thin optical disk so as to stabilize the run-out of the rotating flexible thin optical disk, and a clamper movably supported in a center of the stabilizer member in a direction perpendicular to a surface of the flexible thin optical disk. In the disclosed disk clamping mechanism, the flexible thin optical disk is sandwiched between the turntable and the clamper such that the turntable and the clamper rotate the flexible thin optical member sandwiched in-between.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: October 1, 2013
    Assignees: Ricoh Company, Ltd., Chotaro Engineering Co.
    Inventors: Nobuaki Onagi, Yasutomo Aman, Haruki Tokumaru, Yoshimichi Takano, Daiichi Koide, Takeshi Kajiyama, Masami Nishida
  • Patent number: 8542519
    Abstract: According to one embodiment, a semiconductor memory device is disclosed. The device includes MOSFET1 and MOSFET2 arranged in a first direction, variable resistive element (hereafter R1) above MOSFET1 and MOSFET2, a lower end of the R1 being connected to drains of MOSFET1 and MOSFET2, MOSFET3 and MOSFET4 arranged in the first direction, variable resistive element (hereafter R2) above MOSFET3 and MOSFET4, and a lower end of the R2 being connected to drains of MOSFET3 and MOSFET4. The device further includes first wiring line extending in the first direction and connected to sources of MOSFET1 and MOSFET2, second wiring line extending in the first direction and connected to sources of MOSFET3 and MOSFET4, upper electrode connecting upper end of the R1 and upper end of the R2, and third wiring line extending in the first direction and connected to the upper electrode.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: September 24, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Asao, Takeshi Kajiyama, Kuniaki Sugiura
  • Patent number: 8503216
    Abstract: According to one embodiment, a resistance change type memory includes a memory cell and a capacitor which are provided on a semiconductor substrate. The memory cell includes a resistance change type memory and a select transistor. The resistance change type storage element changes in resistance value in accordance with data to be stored. The select transistor includes a first semiconductor region provided in the semiconductor substrate, and a gate electrode facing the side surface of the first semiconductor region via a gate insulating film. The capacitor includes a second semiconductor region provided in the semiconductor substrate, a capacitor electrode facing the side surface of the second semiconductor region, and a first capacitor insulating film provided between the second semiconductor region and the capacitor electrode.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: August 6, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama
  • Patent number: 8492830
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate having a gate groove and first to third grooves, the first to third grooves being formed on a bottom surface of the gate groove and the third groove being formed between the first and second grooves, and a gate electrode having a first gate portion formed in the first groove, a second gate portion formed in the second groove, a third gate portion formed in the third groove, and a fourth gate portion formed in the gate groove. A cell transistor having the gate electrode has a first channel region formed in the semiconductor substrate between the first and third gate portions and a second channel region formed in the semiconductor substrate between the second and third gate portions.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: July 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama