Patents by Inventor Takeshi Kamino

Takeshi Kamino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10566367
    Abstract: The performances of a semiconductor device are improved. A semiconductor device has a transfer transistor and a photodiode. The photodiode has an n type semiconductor region, an n+ type semiconductor region, and a second p type semiconductor region surrounded by a first p type semiconductor region of an interpixel isolation region. The n+ type semiconductor region is formed on the main surface side of the semiconductor substrate, and the n type semiconductor region is formed under the n+ type semiconductor region via the second p type semiconductor region. In the channel length direction of the transfer transistor, in the n type semiconductor region, an n?? type semiconductor region having a lower impurity density than that of the n type semiconductor region is arranged, to improve the transfer efficiency of electric charges accumulated in the photodiode.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 18, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yotaro Goto, Takeshi Kamino, Fumitoshi Takahashi
  • Patent number: 10559623
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: February 11, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Takahiro Tomimatsu
  • Patent number: 10504950
    Abstract: In order to improve the performance of a solid-state imaging device, the solid-state imaging device has a pixel including a photoelectric conversion unit and a transfer transistor, and fluorine is introduced to a gate electrode and a drain region (extension region and n+-type semiconductor region) of the transfer transistor included in the pixel.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: December 10, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Fumitoshi Takahashi, Yotaro Goto
  • Publication number: 20190280041
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Application
    Filed: May 22, 2019
    Publication date: September 12, 2019
    Inventors: Takeshi Kamino, Takahiro Tomimatsu
  • Publication number: 20190273108
    Abstract: A hybrid-bonding-type solid-state imaging device is provided that prevents moisture from entering through the bonded interface and other areas. The solid-state imaging device includes a first interconnect structure over a sensor substrate and a second interconnect structure over a logic substrate, and the first and second interconnect structures are bonded together. At the bonded surface between the first and second interconnect structures, bonding pads formed in the first interconnect structure are bonded to bonding pads formed in the second interconnect structure. Eighth layer portions of a first seal ring formed in the first interconnect structure are bonded to eighth layer portions of a second seal ring formed in the second interconnect structure.
    Type: Application
    Filed: February 19, 2019
    Publication date: September 5, 2019
    Inventors: Hidenori SATO, Koji IIZUKA, Takeshi KAMINO
  • Patent number: 10319779
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: June 11, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Takahiro Tomimatsu
  • Publication number: 20180358394
    Abstract: In order to improve the performance of a solid-state imaging device, the solid-state imaging device has a pixel including a photoelectric conversion unit and a transfer transistor, and fluorine is introduced to a gate electrode and a drain region (extension region and n+-type semiconductor region) of the transfer transistor included in the pixel.
    Type: Application
    Filed: March 16, 2018
    Publication date: December 13, 2018
    Inventors: Takeshi KAMINO, Fumitoshi TAKAHASHI, Yotaro GOTO
  • Patent number: 10115751
    Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes a pixel including a first active region where a photodiode and a transfer transistor are formed and a second active region for supplying a grounding potential. Over a p-type semiconductor region in the second active region, a plug for supplying the grounding potential is disposed. In an n-type semiconductor region for a drain region of the transfer transistor formed in the first active region, a gettering element is introduced. However, in the p-type semiconductor region in the second active region, the gettering element is not introduced.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: October 30, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Yotaro Goto
  • Publication number: 20180308884
    Abstract: The performances of a semiconductor device are improved. A semiconductor device has a transfer transistor and a photodiode. The photodiode has an n type semiconductor region, an n+ type semiconductor region, and a second p type semiconductor region surrounded by a first p type semiconductor region of an interpixel isolation region. The n+ type semiconductor region is formed on the main surface side of the semiconductor substrate, and the n type semiconductor region is formed under the n+ type semiconductor region via the second p type semiconductor region. In the channel length direction of the transfer transistor, in the n type semiconductor region, an n?? type semiconductor region having a lower impurity density than that of the n type semiconductor region is arranged, to improve the transfer efficiency of electric charges accumulated in the photodiode.
    Type: Application
    Filed: February 20, 2018
    Publication date: October 25, 2018
    Inventors: Yotaro Goto, Takeshi Kamino, Fumitoshi Takahashi
  • Publication number: 20180301503
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Application
    Filed: June 21, 2018
    Publication date: October 18, 2018
    Inventors: Takeshi Kamino, Takahiro Tomimatsu
  • Patent number: 10056420
    Abstract: Provided is a semiconductor device with improved performance. The semiconductor device includes a photodiode having a charge storage layer (n-type semiconductor region) and a surface layer (p-type semiconductor region), and a transfer transistor having a gate electrode and a floating diffusion. The surface layer (p-type semiconductor region) of a second conductive type formed over the charge storage layer (n-type semiconductor region) of a first conductive type includes a first sub-region having a low impurity concentration, and a second sub-region having a high impurity concentration. The first sub-region is arranged closer to the floating diffusion than the second sub-region.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: August 21, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Yotaro Goto
  • Patent number: 10026775
    Abstract: The performances of a semiconductor device are improved. A semiconductor device has a photodiode and a transfer transistor formed in a pixel region. Further, the semiconductor device has a second transistor formed in a peripheral circuit region. The transfer transistor includes a first gate electrode, and a film part formed of a thick hard mask film formed over the first gate electrode. The second transistor includes a second gate electrode, source/drain regions, silicide layers formed at the upper surface of the second gate electrode, and the upper surfaces of the source/drain regions.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: July 17, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Takeshi Kamino
  • Patent number: 10020345
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: July 10, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Takahiro Tomimatsu
  • Publication number: 20180040664
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Application
    Filed: October 19, 2017
    Publication date: February 8, 2018
    Inventors: Takeshi Kamino, Takahiro Tomimatsu
  • Patent number: 9806126
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: October 31, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Takahiro Tomimatsu
  • Publication number: 20170213862
    Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes a pixel including a first active region where a photodiode and a transfer transistor are formed and a second active region for supplying a grounding potential. Over a p-type semiconductor region in the second active region, a plug for supplying the grounding potential is disposed. In an n-type semiconductor region for a drain region of the transfer transistor formed in the first active region, a gettering element is introduced. However, in the p-type semiconductor region in the second active region, the gettering element is not introduced.
    Type: Application
    Filed: November 30, 2016
    Publication date: July 27, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Takeshi KAMINO, Yotaro GOTO
  • Publication number: 20170125478
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Application
    Filed: January 12, 2017
    Publication date: May 4, 2017
    Inventors: Takeshi Kamino, Takahiro Tomimatsu
  • Publication number: 20170084658
    Abstract: Provided is a semiconductor device with improved performance. The semiconductor device includes a photodiode having a charge storage layer (n-type semiconductor region) and a surface layer (p-type semiconductor region), and a transfer transistor having a gate electrode and a floating diffusion. The surface layer (p-type semiconductor region) of a second conductive type formed over the charge storage layer (n-type semiconductor region) of a first conductive type includes a first sub-region having a low impurity concentration, and a second sub-region having a high impurity concentration. The first sub-region is arranged closer to the floating diffusion than the second sub-region.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Takeshi KAMINO, Yotaro GOTO
  • Patent number: 9576993
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: February 21, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Takahiro Tomimatsu
  • Patent number: 9564466
    Abstract: Provided is a semiconductor device with improved performance. The semiconductor device includes a photodiode having a charge storage layer (n-type semiconductor region) and a surface layer (p-type semiconductor region), and a transfer transistor having a gate electrode and a floating diffusion. The surface layer (p-type semiconductor region) of a second conductive type formed over the charge storage layer (n-type semiconductor region) of a first conductive type includes a first sub-region having a low impurity concentration, and a second sub-region having a high impurity concentration. The first sub-region is arranged closer to the floating diffusion than the second sub-region.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: February 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Yotaro Goto