Patents by Inventor Takeshi Kawabata
Takeshi Kawabata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7853954Abstract: A microprocessor executes programs in a pipeline architecture including a task register management unit that, if a switch instruction to a second task is issued when a plurality of units executes a first task, switches a value of a task register to second register information that is used when the second task is executed after the execution of the first task is completed and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.Type: GrantFiled: July 7, 2005Date of Patent: December 14, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyoshi Haruki, Mikio Hashimoto, Takeshi Kawabata
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Publication number: 20100299946Abstract: An alignment mechanism includes: an adjusting plate having first and second adjustment ends parallel to an X axis direction; a probe fixing portion provided to the adjusting plate; a probe fixed to the probe fixing portion; a reinforcing plate having first and second base ends parallel to the X axis direction, displacement of the reinforcing portion in a Y axis direction being restricted; Y-direction adjusting screws for pressing the adjusting plate in the Y axis direction; and adjustment connectors for respectively connecting the first adjustment end with the first base end and the second adjustment end with the second base end. A stylus of the probe is disposed on a line of intersection of a first inclined surface including the first adjustment end and the first base end and a second inclined surface including the second adjustment end and the second base end.Type: ApplicationFiled: May 26, 2010Publication date: December 2, 2010Applicant: MITUTOYO CORPORATIONInventors: Takeshi Kawabata, Takeshi Yamamoto
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Publication number: 20100295186Abstract: A pad (15) is provided on a surface connecting a first substrate (11) of a lower layer module with an upper layer module, the pad is partially covered by an insulating film (20) to form an opening section (3) exposing the pad (15), a first connection terminal (2) is formed on the lower surface of the first substrate (11) of the lower layer module, the planar shape of the opening section (3) is different from the planar shape of the first connection terminal (2), the outer shape of the opening section (3) is larger than the first connection terminal (2), and in a transmissive inspection from above, the shape of the lower end of a second connection terminal (30) spreading in the opening section (3) is not concealed by the other terminal. This configuration enables easy and reliable determination of whether bonding sections are satisfactory by a non-destructive inspection.Type: ApplicationFiled: May 20, 2010Publication date: November 25, 2010Applicant: PANASONIC CORPORATIONInventors: Takeshi Kawabata, Takashi YUI
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Publication number: 20100266122Abstract: An encryption/decryption method comprises by using a generalized Feistel structure in which data is divided into n pieces and mixing processing with key data is performed, diffusion processing, in which data transformation via linear operation is executed, is performed at least once between rounds of the generalized Feistel structure, wherein. As the diffusion processing, linear transformation is performed in which each of n pieces of output data is operated on by two or more pieces of input data. The method is adapted for encryption or decryption.Type: ApplicationFiled: December 11, 2008Publication date: October 21, 2010Applicants: NEC CORPORATION, NEC SOFTWARE HOKURIKU, LTD.Inventors: Tomoyasu Suzaki, Yukiyasu Tsunoo, Hiroyasu Kubo, Maki Shigeri, Teruo Saito, Takeshi Kawabata, Hiroki Nakashima
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Patent number: 7816783Abstract: On a surface of a resin base material (11), a first resin coating film (19) having a larger thickness and a larger area than a second resin coating film (20) formed on the other surface of the resin base material (11) is continuously formed. The second resin coating film (20) is formed so as to be separated into a plurality of portions.Type: GrantFiled: July 25, 2007Date of Patent: October 19, 2010Assignee: Panasonic CorporationInventor: Takeshi Kawabata
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Publication number: 20100148342Abstract: A stacked semiconductor module is made by stacking a second semiconductor device having a second semiconductor chip mounted to the top surface of a second semiconductor substrate above the top surface of a first semiconductor device having a first semiconductor chip mounted to a first semiconductor substrate. The top surface of the first semiconductor substrate is provided with a first connection terminal and the bottom surface of the first semiconductor substrate is provided with an external connection terminal. A region of the bottom surface of the second semiconductor substrate lying opposite to the second semiconductor chip is provided with a second connection terminal. A conductive connecting member connects the first connection terminal to the second connection terminal.Type: ApplicationFiled: February 22, 2010Publication date: June 17, 2010Applicant: Panasonic CorporationInventors: Takeshi KAWABATA, Toshiyuki Fukuda
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Patent number: 7707645Abstract: A microprocessor includes a decryption unit that decrypts information to be utilized by a processor core to obtain plaintext information when the acquired information is encrypted; and a plaintext information storing unit that stores the plaintext information. The microprocessor also includes a protected attribute adding unit that adds a protected attribute indicating one of protection and non-protection to the plaintext information based on whether the decryption has been performed; an access request acquiring unit that acquires an access request to the plaintext information; a request type identifying unit that identifies a type of request of the access request; and an access controlling unit that controls an access to the plaintext information based on the type of request and the protected attribute.Type: GrantFiled: June 23, 2005Date of Patent: April 27, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyoshi Haruki, Mikio Hashimoto, Takeshi Kawabata
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Publication number: 20100096739Abstract: A stacked semiconductor module is made by stacking a second semiconductor device having a second semiconductor chip mounted to the top surface of a second semiconductor substrate above the top surface of a first semiconductor device having a first semiconductor chip mounted to a first semiconductor substrate. The top surface of the first semiconductor substrate is provided with a first connection terminal and the bottom surface of the first semiconductor substrate is provided with an external connection terminal. A region of the bottom surface of the second semiconductor substrate lying opposite to the second semiconductor chip is provided with a second connection terminal. A conductive connecting member connects the first connection terminal to the second connection terminal.Type: ApplicationFiled: December 22, 2009Publication date: April 22, 2010Applicant: PANASONIC CORPORATIONInventors: TAKESHI KAWABATA, TOSHIYUKI FUKUDA
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Patent number: 7667313Abstract: A stacked semiconductor module is made by stacking a second semiconductor device having a second semiconductor chip mounted to the top surface of a second semiconductor substrate above the top surface of a first semiconductor device having a first semiconductor chip mounted to a first semiconductor substrate. The top surface of the first semiconductor substrate is provided with a first connection terminal and the bottom surface of the first semiconductor substrate is provided with an external connection terminal. A region of the bottom surface of the second semiconductor substrate lying opposite to the second semiconductor chip is provided with a second connection terminal. A conductive connecting member connects the first connection terminal to the second connection terminal.Type: GrantFiled: July 24, 2006Date of Patent: February 23, 2010Assignee: Panasonic CorporationInventors: Takeshi Kawabata, Toshiyuki Fukuda
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Patent number: 7586183Abstract: A semiconductor module is formed by alternately stacking resin boards and sheet members. Each of the resin boards includes first buried conductors. A semiconductor chip is mounted on the upper face of each of the resin boards. Each of the sheet members having an opening for accommodating the semiconductor chip and including second buried conductors electrically connected to the first buried conductors. A first resin board located at the bottom is thicker than second resin boards. Each of the sheet members includes an adhesive member covering the upper and side faces of the semiconductor chip.Type: GrantFiled: April 18, 2006Date of Patent: September 8, 2009Assignee: Panasonic CorporationInventors: Takeshi Kawabata, Motoaki Satou, Toshiyuki Fukuda, Toshio Tsuda, Kazuhiro Nobori, Seiichi Nakatani
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Publication number: 20090147490Abstract: In a stacked semiconductor module, a test covering connecting terminals is easily conducted and high reliability is achieved.Type: ApplicationFiled: December 9, 2008Publication date: June 11, 2009Applicant: Panasonic CorporationInventor: Takeshi Kawabata
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Publication number: 20090138729Abstract: A first storage unit stores a plurality of security functions each defining a first protection attribute requiring a storage of a value of an argument for input/output of data. A second storage unit stores a program list describing a second protection attribute of a variable indicating a storage area of the data and an executing procedure of a predetermined process. An identifying unit identifies a third protection attribute of an actual argument for input/output of a security function based on the second protection attribute. When a judging unit judges not all of third protection attributes match with first protection attributes, an output unit outputs error information indicating a mismatch of the protection attributes.Type: ApplicationFiled: November 19, 2008Publication date: May 28, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mikio Hashimoto, Hiroyoshi Haruki, Yurie Fujimatsu, Takeshi Kawabata
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Patent number: 7498668Abstract: A lower module of a stacked semiconductor device includes a first substrate and a first semiconductor chip held above the first substrate. The top surface of the first substrate is provided with a plurality of first chip connection terminals electrically connected to the first chip terminals, respectively, and a plurality of upper module connection terminals electrically connectable to an upper module provided with a second semiconductor chip. The back surface of the first substrate is provided with a plurality of external substrate connection terminals. Each of the first chip connection terminals is electrically connected to a corresponding one of the external substrate connection terminals, and each of the upper module connection terminals is electrically connected between a corresponding one of the chip connection terminals and a corresponding one of the external substrate connection terminals.Type: GrantFiled: June 27, 2006Date of Patent: March 3, 2009Assignee: Panasonic CorporationInventors: Takeshi Kawabata, Fumito Itou
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Patent number: 7443028Abstract: An imaging module is formed by stacking: a first resin board; a second resin board having a first opening; a first electrically-conductive member electrically connecting the first resin board and the second resin board to each other; a printed circuit board having a second opening; a second electrically-conductive member electrically connecting the second resin board and the printed circuit board to each other; an imaging semiconductor chip mounted on the lower surface of the second resin board to cover the first opening and provided with an imaging sensor, an optical member placed on the upper surface of the second resin board to cover the first opening; a first semiconductor control chip provided with a control device for controlling operation of the imaging sensor and mounted on the lower surface of the first resin board.Type: GrantFiled: March 8, 2006Date of Patent: October 28, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Motoaki Satou, Takeshi Kawabata, Masatoshi Shinagawa, Toshiyuki Fukuda
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Patent number: 7365416Abstract: A semiconductor module is formed by alternately stacking resin boards 3 on which semiconductor chips 2 are mounted and sheet members having openings larger than the semiconductor chips 2 and bonded to the resin boards 3. The resin board 4 located at the bottom out of the resin boards 3 is thicker than the other resin boards 3.Type: GrantFiled: October 5, 2005Date of Patent: April 29, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeshi Kawabata, Motoaki Satou, Toshiyuki Fukuda, Toshio Tsuda, Kazuhiro Nobori, Seiichi Nakatani
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Publication number: 20080067661Abstract: On a surface of a resin base material (11), a first resin coating film (19) having a larger thickness and a larger area than a second resin coating film (20) formed on the other surface of the resin base material (11) is continuously formed. The second resin coating film (20) is formed so as to be separated into a plurality of portions.Type: ApplicationFiled: July 25, 2007Publication date: March 20, 2008Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Takeshi Kawabata
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Patent number: 7327021Abstract: A semiconductor module is formed by alternately stacking resin boards on which semiconductor chips are mounted and sheet members having openings larger than the semiconductor chips and bonded to the resin boards. One of the resin boards located at the bottom has a thickness larger than that of each of the other resin boards. First buried conductors formed in each of first resin boards are arranged to form a plurality of lines surrounding a region on which a semiconductor chip is to be mounted. The spacing between the first buried conductors increases in succession toward the outermost line. Second buried conductors formed in each of sheet members are arranged to form a plurality of lines surrounding an opening. The spacing between the second buried conductors increases in succession toward the outermost line.Type: GrantFiled: November 9, 2006Date of Patent: February 5, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Motoaki Satou, Takeshi Kawabata, Toshiyuki Fukuda
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Publication number: 20070138619Abstract: In a substrate for a stacking-type semiconductor device including a connection terminal provided for a connection with a semiconductor chip to be stacked and an external terminal connected to the connection terminal through a conductor provided in a substrate, connection terminals of a power supply, a ground and the like, which terminals have an identical node, are electrically continuous with each other. Thus, it is possible to facilitate an inspection of electrical continuity between each connection terminal and an external terminal corresponding to each connection terminal by minimum addition of inspecting terminals. Further, it is possible to improve reliability of a stacking-type semiconductor module.Type: ApplicationFiled: October 25, 2006Publication date: June 21, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Masatoshi Shinagawa, Takeshi Kawabata
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Publication number: 20070096291Abstract: A lower module of a stacked semiconductor device includes a first substrate and a first semiconductor chip held above the first substrate. The top surface of the first substrate is provided with a plurality of first chip connection terminals electrically connected to the first chip terminals, respectively, and a plurality of upper module connection terminals electrically connectable to an upper module provided with a second semiconductor chip. The back surface of the first substrate is provided with a plurality of external substrate connection terminals. Each of the first chip connection terminals is electrically connected to a corresponding one of the external substrate connection terminals, and each of the upper module connection terminals is electrically connected between a corresponding one of the chip connection terminals and a corresponding one of the external substrate connection terminals.Type: ApplicationFiled: June 27, 2006Publication date: May 3, 2007Inventors: Takeshi Kawabata, Fumito Itou
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Publication number: 20070096334Abstract: A stacked semiconductor module is made by stacking a second semiconductor device having a second semiconductor chip mounted to the top surface of a second semiconductor substrate above the top surface of a first semiconductor device having a first semiconductor chip mounted to a first semiconductor substrate. The top surface of the first semiconductor substrate is provided with a first connection terminal and the bottom surface of the first semiconductor substrate is provided with an external connection terminal. A region of the bottom surface of the second semiconductor substrate lying opposite to the second semiconductor chip is provided with a second connection terminal. A conductive connecting member connects the first connection terminal to the second connection terminal.Type: ApplicationFiled: July 24, 2006Publication date: May 3, 2007Inventors: Takeshi Kawabata, Toshiyuki Fukuda