Patents by Inventor Takeshi Matsunuma
Takeshi Matsunuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929380Abstract: There is provided a solid-state image-capturing element capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.Type: GrantFiled: October 14, 2021Date of Patent: March 12, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yusuke Tanaka, Takashi Nagano, Toshifumi Wakano, Takeshi Matsunuma
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Publication number: 20230300492Abstract: Provided is a method for manufacturing a light detection device capable of suppressing optical color mixing while improving sensitivity. On a substrate in which a plurality of photoelectric conversion units is formed, anisotropic etching is performed from one surface side of the substrate to form a plurality of openings arranged in a lattice shape at predetermined intervals on the substrate to surround each photoelectric conversion unit. Subsequently, isotropic etching is performed from one surface side of the substrate to connect adjacent openings to each other, to form a lattice-shaped trench part on the substrate to surround each photoelectric conversion unit.Type: ApplicationFiled: June 3, 2021Publication date: September 21, 2023Inventors: TERUMI KAMBE, TAKESHI MATSUNUMA
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Patent number: 11457201Abstract: An imaging device capable of further increasing the accuracy of distance information and an electronic apparatus equipped with the imaging device are provided. The present technology provides an imaging device that includes a stereo imager, and the stereo imager includes a plurality of sensors. Each sensor of the plurality of sensors has an imaging unit formed with a plurality of repeating units. The imaging unit includes a polarizer having at least one kind of polarization spindle angle, and at least two unit images obtained by a plurality of the imaging units are combined, to obtain information about polarization in at least three directions, and generate normal information. The present technology further provides an electronic apparatus equipped with the imaging device.Type: GrantFiled: February 27, 2019Date of Patent: September 27, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takeshi Matsunuma, Motonari Honda
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Patent number: 11424279Abstract: In an imaging element, a plurality of pixels each having a photoelectric conversion part is arranged in a two-dimensional matrix. Some of the plurality of pixels each have a polarizer placed therein on a side of a light beam incidence plane. At least some of pixels having no polarizer placed therein each have a material layer placed therein that prevents transmission of a light beam having a wavelength of a predetermined range, to reduce color mixture in the pixel having the polarizer placed therein.Type: GrantFiled: March 20, 2018Date of Patent: August 23, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Takeshi Matsunuma, Motonari Honda
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Publication number: 20220149103Abstract: Provided are a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.Type: ApplicationFiled: November 18, 2021Publication date: May 12, 2022Inventors: YUSUKE TANAKA, TAKASHI NAGANO, TOSHIFUMI WAKANO, TAKESHI MATSUNUMA
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Publication number: 20220037389Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.Type: ApplicationFiled: October 14, 2021Publication date: February 3, 2022Inventors: YUSUKE TANAKA, TAKASHI NAGANO, TOSHIFUMI WAKANO, TAKESHI MATSUNUMA
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Publication number: 20220007001Abstract: An imaging device capable of further increasing the accuracy of distance information and an electronic apparatus equipped with the imaging device are provided. The present technology provides an imaging device that includes a stereo imager, and the stereo imager includes a plurality of sensors. Each sensor of the plurality of sensors has an imaging unit formed with a plurality of repeating units. The imaging unit includes a polarizer having at least one kind of polarization spindle angle, and at least two unit images obtained by a plurality of the imaging units are combined, to obtain information about polarization in at least three directions, and generate normal information. The present technology further provides an electronic apparatus equipped with the imaging device.Type: ApplicationFiled: February 27, 2019Publication date: January 6, 2022Inventors: TAKESHI MATSUNUMA, MOTONARI HONDA
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Patent number: 11183528Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.Type: GrantFiled: September 9, 2020Date of Patent: November 23, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yusuke Tanaka, Takashi Nagano, Toshifumi Wakano, Takeshi Matsunuma
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Publication number: 20210233946Abstract: The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.Type: ApplicationFiled: April 13, 2021Publication date: July 29, 2021Applicant: SONY GROUP CORPORATIONInventors: Rena SUZUKI, Takeshi MATSUNUMA, Naoki JYO, Yoshihisa KAGAWA
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Patent number: 11004879Abstract: The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.Type: GrantFiled: February 19, 2020Date of Patent: May 11, 2021Assignee: SONY CORPORATIONInventors: Rena Suzuki, Takeshi Matsunuma, Naoki Jyo, Yoshihisa Kagawa
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Publication number: 20210118931Abstract: In an imaging element, a plurality of pixels each having a photoelectric conversion part is arranged in a two-dimensional matrix. Some of the plurality of pixels each have a polarizer placed therein on a side of a light beam incidence plane. At least some of pixels having no polarizer placed therein each have a material layer placed therein that prevents transmission of a light beam having a wavelength of a predetermined range, to reduce color mixture in the pixel having the polarizer placed therein.Type: ApplicationFiled: March 20, 2018Publication date: April 22, 2021Inventors: Takeshi Matsunuma, Motonari Honda
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Publication number: 20200403021Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.Type: ApplicationFiled: September 9, 2020Publication date: December 24, 2020Inventors: Yusuke Tanaka, Takashi Nagano, Toshifumi Wakano, Takeshi Matsunuma
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Patent number: 10797097Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.Type: GrantFiled: July 10, 2019Date of Patent: October 6, 2020Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yusuke Tanaka, Takashi Nagano, Toshifumi Wakano, Takeshi Matsunuma
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Publication number: 20200185433Abstract: The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.Type: ApplicationFiled: February 19, 2020Publication date: June 11, 2020Applicant: SONY CORPORATIONInventors: Rena SUZUKI, Takeshi MATSUNUMA, Naoki JYO, Yoshihisa KAGAWA
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Patent number: 10665623Abstract: The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.Type: GrantFiled: February 12, 2016Date of Patent: May 26, 2020Assignee: SONY CORPORATIONInventors: Rena Suzuki, Takeshi Matsunuma, Naoki Jyo, Yoshihisa Kagawa
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Patent number: 10665629Abstract: The present technology relates to an imaging device designed to be able to reduce luminance unevenness. An imaging device includes a photodiode and a wiring layer formed on a surface facing the incident surface of the photodiode. A wiring line is formed in the wiring layer, and the wiring line in a pixel is formed in a different pattern from a pattern in a different pixel. Another imaging device including a photodiode and a wiring layer formed on a surface facing the incident surface of the photodiode. A wiring line is formed in the wiring layer. A gap having a different dielectric constant from the dielectric constant of the material forming the wiring layer is formed in the wiring layer, and the gap in a pixel is formed in a different pattern from a pattern in a different pixel. The present technology can be applied to imaging devices.Type: GrantFiled: February 10, 2017Date of Patent: May 26, 2020Assignee: SONY CORPORATIONInventors: Motonari Honda, Ryoji Suzuki, Takeshi Matsunuma
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Publication number: 20200006417Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.Type: ApplicationFiled: July 10, 2019Publication date: January 2, 2020Inventors: YUSUKE TANAKA, TAKASHI NAGANO, TOSHIFUMI WAKANO, TAKESHI MATSUNUMA
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Patent number: 10396116Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.Type: GrantFiled: March 17, 2016Date of Patent: August 27, 2019Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yusuke Tanaka, Takashi Nagano, Toshifumi Wakano, Takeshi Matsunuma
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Patent number: 10373994Abstract: There is provided an image sensor having a plurality of pixels, each pixel including a light receiving portion configured to receive incident light, a waveguide configured to guide the incident light from a light incident surface to the light receiving portion, and a light shielding portion disposed between the light incident surface and the light receiving portion, for blocking the incident light. The light shielding portion has an opening formed near a light emitting surface of the waveguide. The light receiving portion receives the incident light passing through the waveguide and the opening. A width of a core of the waveguide and a width of the opening are set so that the widths increase as a wavelength of the light incident on a pixel becomes longer.Type: GrantFiled: August 21, 2013Date of Patent: August 6, 2019Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshiaki Masuda, Takeshi Matsunuma
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Publication number: 20190043911Abstract: The present technology relates to an imaging device designed to be able to reduce luminance unevenness. An imaging device includes a photodiode and a wiring layer formed on a surface facing the incident surface of the photodiode. A wiring line is formed in the wiring layer, and the wiring line in a pixel is formed in a different pattern from a pattern in a different pixel. Another imaging device including a photodiode and a wiring layer formed on a surface facing the incident surface of the photodiode. A wiring line is formed in the wiring layer. A gap having a different dielectric constant from the dielectric constant of the material forming the wiring layer is formed in the wiring layer, and the gap in a pixel is formed in a different pattern from a pattern in a different pixel. The present technology can be applied to imaging devices.Type: ApplicationFiled: February 10, 2017Publication date: February 7, 2019Applicant: SONY CORPORATIONInventors: MOTONARI HONDA, RYOJI SUZUKI, TAKESHI MATSUNUMA