Patents by Inventor Takeshi Matsunuma

Takeshi Matsunuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11929380
    Abstract: There is provided a solid-state image-capturing element capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: March 12, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke Tanaka, Takashi Nagano, Toshifumi Wakano, Takeshi Matsunuma
  • Publication number: 20230300492
    Abstract: Provided is a method for manufacturing a light detection device capable of suppressing optical color mixing while improving sensitivity. On a substrate in which a plurality of photoelectric conversion units is formed, anisotropic etching is performed from one surface side of the substrate to form a plurality of openings arranged in a lattice shape at predetermined intervals on the substrate to surround each photoelectric conversion unit. Subsequently, isotropic etching is performed from one surface side of the substrate to connect adjacent openings to each other, to form a lattice-shaped trench part on the substrate to surround each photoelectric conversion unit.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 21, 2023
    Inventors: TERUMI KAMBE, TAKESHI MATSUNUMA
  • Patent number: 11457201
    Abstract: An imaging device capable of further increasing the accuracy of distance information and an electronic apparatus equipped with the imaging device are provided. The present technology provides an imaging device that includes a stereo imager, and the stereo imager includes a plurality of sensors. Each sensor of the plurality of sensors has an imaging unit formed with a plurality of repeating units. The imaging unit includes a polarizer having at least one kind of polarization spindle angle, and at least two unit images obtained by a plurality of the imaging units are combined, to obtain information about polarization in at least three directions, and generate normal information. The present technology further provides an electronic apparatus equipped with the imaging device.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 27, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takeshi Matsunuma, Motonari Honda
  • Patent number: 11424279
    Abstract: In an imaging element, a plurality of pixels each having a photoelectric conversion part is arranged in a two-dimensional matrix. Some of the plurality of pixels each have a polarizer placed therein on a side of a light beam incidence plane. At least some of pixels having no polarizer placed therein each have a material layer placed therein that prevents transmission of a light beam having a wavelength of a predetermined range, to reduce color mixture in the pixel having the polarizer placed therein.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: August 23, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Takeshi Matsunuma, Motonari Honda
  • Publication number: 20220149103
    Abstract: Provided are a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 12, 2022
    Inventors: YUSUKE TANAKA, TAKASHI NAGANO, TOSHIFUMI WAKANO, TAKESHI MATSUNUMA
  • Publication number: 20220037389
    Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.
    Type: Application
    Filed: October 14, 2021
    Publication date: February 3, 2022
    Inventors: YUSUKE TANAKA, TAKASHI NAGANO, TOSHIFUMI WAKANO, TAKESHI MATSUNUMA
  • Publication number: 20220007001
    Abstract: An imaging device capable of further increasing the accuracy of distance information and an electronic apparatus equipped with the imaging device are provided. The present technology provides an imaging device that includes a stereo imager, and the stereo imager includes a plurality of sensors. Each sensor of the plurality of sensors has an imaging unit formed with a plurality of repeating units. The imaging unit includes a polarizer having at least one kind of polarization spindle angle, and at least two unit images obtained by a plurality of the imaging units are combined, to obtain information about polarization in at least three directions, and generate normal information. The present technology further provides an electronic apparatus equipped with the imaging device.
    Type: Application
    Filed: February 27, 2019
    Publication date: January 6, 2022
    Inventors: TAKESHI MATSUNUMA, MOTONARI HONDA
  • Patent number: 11183528
    Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: November 23, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke Tanaka, Takashi Nagano, Toshifumi Wakano, Takeshi Matsunuma
  • Publication number: 20210233946
    Abstract: The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Applicant: SONY GROUP CORPORATION
    Inventors: Rena SUZUKI, Takeshi MATSUNUMA, Naoki JYO, Yoshihisa KAGAWA
  • Patent number: 11004879
    Abstract: The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: May 11, 2021
    Assignee: SONY CORPORATION
    Inventors: Rena Suzuki, Takeshi Matsunuma, Naoki Jyo, Yoshihisa Kagawa
  • Publication number: 20210118931
    Abstract: In an imaging element, a plurality of pixels each having a photoelectric conversion part is arranged in a two-dimensional matrix. Some of the plurality of pixels each have a polarizer placed therein on a side of a light beam incidence plane. At least some of pixels having no polarizer placed therein each have a material layer placed therein that prevents transmission of a light beam having a wavelength of a predetermined range, to reduce color mixture in the pixel having the polarizer placed therein.
    Type: Application
    Filed: March 20, 2018
    Publication date: April 22, 2021
    Inventors: Takeshi Matsunuma, Motonari Honda
  • Publication number: 20200403021
    Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 24, 2020
    Inventors: Yusuke Tanaka, Takashi Nagano, Toshifumi Wakano, Takeshi Matsunuma
  • Patent number: 10797097
    Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: October 6, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke Tanaka, Takashi Nagano, Toshifumi Wakano, Takeshi Matsunuma
  • Publication number: 20200185433
    Abstract: The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.
    Type: Application
    Filed: February 19, 2020
    Publication date: June 11, 2020
    Applicant: SONY CORPORATION
    Inventors: Rena SUZUKI, Takeshi MATSUNUMA, Naoki JYO, Yoshihisa KAGAWA
  • Patent number: 10665623
    Abstract: The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 26, 2020
    Assignee: SONY CORPORATION
    Inventors: Rena Suzuki, Takeshi Matsunuma, Naoki Jyo, Yoshihisa Kagawa
  • Patent number: 10665629
    Abstract: The present technology relates to an imaging device designed to be able to reduce luminance unevenness. An imaging device includes a photodiode and a wiring layer formed on a surface facing the incident surface of the photodiode. A wiring line is formed in the wiring layer, and the wiring line in a pixel is formed in a different pattern from a pattern in a different pixel. Another imaging device including a photodiode and a wiring layer formed on a surface facing the incident surface of the photodiode. A wiring line is formed in the wiring layer. A gap having a different dielectric constant from the dielectric constant of the material forming the wiring layer is formed in the wiring layer, and the gap in a pixel is formed in a different pattern from a pattern in a different pixel. The present technology can be applied to imaging devices.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: May 26, 2020
    Assignee: SONY CORPORATION
    Inventors: Motonari Honda, Ryoji Suzuki, Takeshi Matsunuma
  • Publication number: 20200006417
    Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 2, 2020
    Inventors: YUSUKE TANAKA, TAKASHI NAGANO, TOSHIFUMI WAKANO, TAKESHI MATSUNUMA
  • Patent number: 10396116
    Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: August 27, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke Tanaka, Takashi Nagano, Toshifumi Wakano, Takeshi Matsunuma
  • Patent number: 10373994
    Abstract: There is provided an image sensor having a plurality of pixels, each pixel including a light receiving portion configured to receive incident light, a waveguide configured to guide the incident light from a light incident surface to the light receiving portion, and a light shielding portion disposed between the light incident surface and the light receiving portion, for blocking the incident light. The light shielding portion has an opening formed near a light emitting surface of the waveguide. The light receiving portion receives the incident light passing through the waveguide and the opening. A width of a core of the waveguide and a width of the opening are set so that the widths increase as a wavelength of the light incident on a pixel becomes longer.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: August 6, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yoshiaki Masuda, Takeshi Matsunuma
  • Publication number: 20190043911
    Abstract: The present technology relates to an imaging device designed to be able to reduce luminance unevenness. An imaging device includes a photodiode and a wiring layer formed on a surface facing the incident surface of the photodiode. A wiring line is formed in the wiring layer, and the wiring line in a pixel is formed in a different pattern from a pattern in a different pixel. Another imaging device including a photodiode and a wiring layer formed on a surface facing the incident surface of the photodiode. A wiring line is formed in the wiring layer. A gap having a different dielectric constant from the dielectric constant of the material forming the wiring layer is formed in the wiring layer, and the gap in a pixel is formed in a different pattern from a pattern in a different pixel. The present technology can be applied to imaging devices.
    Type: Application
    Filed: February 10, 2017
    Publication date: February 7, 2019
    Applicant: SONY CORPORATION
    Inventors: MOTONARI HONDA, RYOJI SUZUKI, TAKESHI MATSUNUMA