Patents by Inventor Takeshi MISHINA

Takeshi MISHINA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12254402
    Abstract: An optimization device includes: a memory; and a processor configured to: perform, as annealing operations, a process including, with respect to a change in a value of any of state variables included in an evaluation function representing an energy, based on a change in the energy, determining which change of value of the state variables is accepted, and determining a value of each of the state variables; retain correspondence information in which identification information that identifies the annealing operations is arranged; cause start of the process by each of the annealing operations, determine whether or not to perform, when the processes by two of the annealing operations corresponding to two temperatures are completed, exchange of the temperatures assigned to the two annealing operations; update the correspondence information when performing the exchange; and supply temperature information representing the temperatures to the two annealing operations.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: March 18, 2025
    Assignee: FUJITSU LIMITED
    Inventors: Masato Sasaki, Takeshi Mishina, Satoshi Matsuura
  • Patent number: 11886780
    Abstract: An optimization device includes: a memory; and a processor and configured to: store a coefficient indicating magnitude of an interaction between bits in a bit string representing a state of an Ising model; output, when any bit in the bit string is inverted, a signal indicating inversion availability of an own bit according to calculation of energy change in the Ising model using the coefficient corresponding to the inverted bit and the own bit read from the memory as bit operations; output a signal indicating a bit to be inverted in the bit string selected on the basis of the signal indicating inversion availability output from bit operations of a first number of bits of the bit string, of the bit operations; and change the first number of bits and change a second number of bits of the coefficient for each bit operations of the first number of bits.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: January 30, 2024
    Assignee: FUJITSU LIMITED
    Inventors: Takeshi Mishina, Yoshimasa Tani, Satoshi Matsuura
  • Patent number: 11443090
    Abstract: An optimization device includes: a memory; and a processor configured to: calculate, as bit operations, when any bit in a bit string representing a state of an Ising model is inverted, an energy change value of the Ising model based on a coefficient indicating magnitude of an interaction between an own bit and the inverted bit in the bit string; output a first signal indicating inversion availability of the own bit according to the energy change value and a second signal indicating the energy change value; select the bit to be inverted in the bit string and the energy change value corresponding to the bit based on the first signal and the second signal; output a fourth signal indicating the selected energy change value; and calculate energy of the Ising model based on the energy change value indicated by the fourth signal.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: September 13, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Takeshi Mishina, Satoshi Matsuura
  • Publication number: 20210334680
    Abstract: An optimization apparatus includes a processor. The processor configured to calculate a change amount of energy represented by an evaluation function of a case of changing a state of any one of a plurality of state variables so as to increase or decrease a value by 1 in a case of a state variable taking multiple values, the evaluation function representing the energy including the plurality of state variables, determine whether to set a state change in the state variable as a candidate according to a correlation between a threshold and a total change amount, stochastically determine whether to adopt the state change set as the candidate, calculate post-transition energy after executing a state transition of the state variable according to the state change, and obtain minimum energy by setting the post-transition energy as the minimum energy when the post-transition energy is less than the minimum energy.
    Type: Application
    Filed: March 2, 2021
    Publication date: October 28, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Satoshi MATSUURA, Takeshi Mishina
  • Publication number: 20210173990
    Abstract: An optimization device includes: a memory; and a processor configured to: calculate, as bit operations, when any bit in a bit string representing a state of an Ising model is inverted, an energy change value of the Ising model based on a coefficient indicating magnitude of an interaction between an own bit and the inverted bit in the bit string; output a first signal indicating inversion availability of the own bit according to the energy change value and a second signal indicating the energy change value; select the bit to be inverted in the bit string and the energy change value corresponding to the bit based on the first signal and the second signal; output a fourth signal indicating the selected energy change value; and calculate energy of the Ising model based on the energy change value indicated by the fourth signal.
    Type: Application
    Filed: February 18, 2021
    Publication date: June 10, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Mishina, Satoshi MATSUURA
  • Publication number: 20210173978
    Abstract: An optimization device includes: a memory; and a processor and configured to: store a coefficient indicating magnitude of an interaction between bits in a bit string representing a state of an Ising model; output, when any bit in the bit string is inverted, a signal indicating inversion availability of an own bit according to calculation of energy change in the Ising model using the coefficient corresponding to the inverted bit and the own bit read from the memory as bit operations; output a signal indicating a bit to be inverted in the bit string selected on the basis of the signal indicating inversion availability output from bit operations of a first number of bits of the bit string, of the bit operations; and change the first number of bits and change a second number of bits of the coefficient for each bit operations of the first number of bits.
    Type: Application
    Filed: February 19, 2021
    Publication date: June 10, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Mishina, Yoshimasa Tani, Satoshi Matsuura
  • Publication number: 20210150356
    Abstract: An optimization device includes: a memory; and a processor configured to: perform, as annealing operations, a process including, with respect to a change in a value of any of state variables included in an evaluation function representing an energy, based on a change in the energy, determining which change of value of the state variables is accepted, and determining a value of each of the state variables; retain correspondence information in which identification information that identifies the annealing operations is arranged; cause start of the process by each of the annealing operations, determine whether or not to perform, when the processes by two of the annealing operations corresponding to two temperatures are completed, exchange of the temperatures assigned to the two annealing operations; update the correspondence information when performing the exchange; and supply temperature information representing the temperatures to the two annealing operations.
    Type: Application
    Filed: January 28, 2021
    Publication date: May 20, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Masato Sasaki, Takeshi Mishina, Satoshi MATSUURA
  • Patent number: 10775870
    Abstract: A processing device includes multiple processing units and multiple memory devices respectively assigned to the multiple processing units. Each of the multiple processing units includes a cache memory configured to retain data stored in the memory device assigned to itself, and fetched data taken out from the memory device of the processing unit other than itself. When an access request for the fetched data is received from a source processing unit from which the fetched data has been taken out, the cache memory determines occurrence of a crossing in which the access request is received after the cache memory issues write back information instructing to write back the fetched data to the memory device assigned to the source processing unit. If the crossing has occurred, crossing information indicating that the crossing has occurred is output as a response to the access request.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 15, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takeshi Mishina, Hideki Sakata
  • Publication number: 20180335829
    Abstract: A processing device includes multiple processing units and multiple memory devices respectively assigned to the multiple processing units. Each of the multiple processing units includes a cache memory configured to retain data stored in the memory device assigned to itself, and fetched data taken out from the memory device of the processing unit other than itself. When an access request for the fetched data is received from a source processing unit from which the fetched data has been taken out, the cache memory determines occurrence of a crossing in which the access request is received after the cache memory issues write back information instructing to write back the fetched data to the memory device assigned to the source processing unit. If the crossing has occurred, crossing information indicating that the crossing has occurred is output as a response to the access request.
    Type: Application
    Filed: May 7, 2018
    Publication date: November 22, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi MISHINA, Hideki SAKATA