Patents by Inventor Takeshi Sakata
Takeshi Sakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240075011Abstract: A method for treating amyotrophic lateral sclerosis includes administering an effective amount of 3-methyl-1-phenyl-2-pyrazolin-5-one or a physiologically acceptable salt thereof to a patient who is in need thereof and meets two or more features selected from a group of identified features.Type: ApplicationFiled: November 2, 2023Publication date: March 7, 2024Applicant: MITSUBISHI TANABE PHARMA CORPORATIONInventors: Charlotte MERRILL, Wendy AGNESE, Nazem ATASSI, Tara GRABOWSKY, Takeshi SAKATA
-
Publication number: 20230355163Abstract: A neuromuscular disease evaluation device that is less invasive, highly sensitive, quantitative and objective, and capable of easily evaluating neuromuscular diseases. A device for evaluating motor functions related to neuromuscular diseases, comprising: a memory unit storing a reference value for evaluating a predetermined movement, which is calculated based on a position of at least one body part; an analysis unit for identifying a position of a body part of the user by analyzing information based on an image captured of the predetermined movement, including the user's body; and an evaluation unit for evaluating the motor function based on the numerical value calculated based on the position of the body part of the user and the reference value.Type: ApplicationFiled: September 29, 2021Publication date: November 9, 2023Inventors: Takeshi SAKATA, Akiko GOTO, Atsushi KATO, Manabu HIRAI
-
Publication number: 20210145798Abstract: A method for treating amyotrophic lateral sclerosis includes administering an effective amount of 3-methyl-1-phenyl-2-pyrazolin-5-one or a physiologically acceptable salt thereof to a patient who is in need thereof and meets two or more features selected from a group of identified features.Type: ApplicationFiled: October 4, 2018Publication date: May 20, 2021Applicant: MITSUBISHI TANABE PHARMA CORPORATIONInventors: Charlotte MERRILL, Wendy AGNESE, Nazem ATASSI, Tara GRABOWSKY, Takeshi SAKATA
-
Patent number: 10418875Abstract: A thermal insulation structure for an electronic device of the present invention is a thermal insulation structure which thermally insulates between an electronic circuit unit and a heat generator formed with another component. In the thermal insulation structure, a partition wall for separating each space and formed of resin having electric insulation properties is provided between the electronic circuit unit and the heat generator. Also, the partition wall is formed by integrating the resin and a thermal insulation material having thermal conductivity lower than thermal conductivity of air so that the resin includes the thermal insulation material. Further, the partition wall is formed by insert-molding the thermal insulation material with the resin. Further, the resin having the electric insulation properties is thermoplastic resin, and a thermal insulation raw material of the thermal insulation material is silica xerogel.Type: GrantFiled: July 29, 2015Date of Patent: September 17, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yuichiro Sadanaga, Kenji Kondo, Takeshi Sakata, Masanori Morita
-
Publication number: 20180260687Abstract: Efficient learning of a neural network can be performed. A plurality of DNNs are hierarchically configured, and data of a hidden layer of a DNN of a first hierarchy machine learning/recognizing device is used as input data of a DNN of a second hierarchy machine learning/recognizing device.Type: ApplicationFiled: April 26, 2016Publication date: September 13, 2018Inventors: Yusuke KANNO, Takeshi SAKATA, Shigeru NAKAHARA
-
Patent number: 10033357Abstract: Provided is a semiconductor device capable of reducing a penalty associated with ensuring reliability. The semiconductor device includes a latch circuit which has input/output paths of three systems or more independent from each other. The latch circuit includes a plurality of storage elements STE1 to STE3 which are provided on the input/output paths of the three systems or more, respectively, and hold input data in synchronization with a clock signal. At least one storage element (for example, STE1) of the plurality of storage elements STE1 to STE3 includes a majority decision unit (for example, 81a) executing a majority decision using data from the storage elements provided on other input/output paths different from the input/output path thereof and outputs data in which a result of the majority decision is reflected.Type: GrantFiled: October 16, 2013Date of Patent: July 24, 2018Assignee: Hitachi, Ltd.Inventors: Yusuke Kanno, Takeshi Sakata, Nobuyasu Kanekawa
-
Publication number: 20170194829Abstract: A thermal insulation structure for an electronic device of the present invention is a thermal insulation structure which thermally insulates between an electronic circuit unit and a heat generator formed with another component. In the thermal insulation structure, a partition wall for separating each space and formed of resin having electric insulation properties is provided between the electronic circuit unit and the heat generator. Also, the partition wall is formed by integrating the resin and a thermal insulation material having thermal conductivity lower than thermal conductivity of air so that the resin includes the thermal insulation material. Further, the partition wall is formed by insert-molding the thermal insulation material with the resin. Further, the resin having the electric insulation properties is thermoplastic resin, and a thermal insulation raw material of the thermal insulation material is silica xerogel.Type: ApplicationFiled: July 29, 2015Publication date: July 6, 2017Inventors: YUICHIRO SADANAGA, KENJI KONDO, TAKESHI SAKATA, MASANORI MORITA
-
Publication number: 20160254803Abstract: Provided is a semiconductor device capable of reducing a penalty associated with ensuring reliability. The semiconductor device includes a latch circuit which has input/output paths of three systems or more independent from each other. The latch circuit includes a plurality of storage elements STE1 to STE3 which are provided on the input/output paths of the three systems or more, respectively, and hold input data in synchronization with a clock signal. At least one storage element (for example, STE1) of the plurality of storage elements STE1 to STE3 includes a majority decision unit (for example, 81a) executing a majority decision using data from the storage elements provided on other input/output paths different from the input/output path thereof and outputs data in which a result of the majority decision is reflected.Type: ApplicationFiled: October 16, 2013Publication date: September 1, 2016Inventors: Yusuke KANNO, Takeshi SAKATA, Nobuyasu KANEKAWA
-
Patent number: 9337838Abstract: In a device including a programmable circuit, the programmable circuit is connected to a non-volatile memory in which configuration information is stored, and another memory having a faster reading speed than the non-volatile memory, and the programmable circuit includes a configuration memory control circuit, and a signal line group for performing reading with respect to the other memory such as a volatile memory and an embedded memory from the non-volatile memory by the configuration memory control circuit, and copies a part of circuit configuration information which is required to be subjected to fast restoration from failure into the other memory.Type: GrantFiled: January 9, 2015Date of Patent: May 10, 2016Assignee: Hitachi, Ltd.Inventors: Makoto Saen, Takeshi Sakata, Masashi Ohkawa, Yusuke Kanno
-
Publication number: 20150236696Abstract: In a device including a programmable circuit, the programmable circuit is connected to a non-volatile memory in which configuration information is stored, and another memory having a faster reading speed than the non-volatile memory, and the programmable circuit includes a configuration memory control circuit, and a signal line group for performing reading with respect to the other memory such as a volatile memory and an embedded memory from the non-volatile memory by the configuration memory control circuit, and copies a part of circuit configuration information which is required to be subjected to fast restoration from failure into the other memory.Type: ApplicationFiled: January 9, 2015Publication date: August 20, 2015Inventors: MAKOTO SAEN, TAKESHI SAKATA, MASASHI OHKAWA, YUSUKE KANNO
-
Patent number: 8605478Abstract: In a sense circuit for DRAM memory cell a switch is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.Type: GrantFiled: May 23, 2012Date of Patent: December 10, 2013Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Hiroyuki Mizuno, Takeshi Sakata, Nobuhiro Oodaira, Takao Watanabe, Yusuke Kanno
-
Publication number: 20120294081Abstract: In a sense circuit for DRAM memory cell a switch is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.Type: ApplicationFiled: May 23, 2012Publication date: November 22, 2012Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATIONInventors: HIROYUKI MIZUNO, TAKESHI SAKATA, NOBUHIRO OODAIRA, TAKAO WATANABE, YUSUKE KANNO
-
Patent number: 8199549Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data.Type: GrantFiled: August 19, 2010Date of Patent: June 12, 2012Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Hiroyuki Mizuno, Takeshi Sakata, Nobuhiro Oodaira, Takao Watanabe, Yusuke Kanno
-
Patent number: 8138442Abstract: Provided are a wire electric discharge machining method for poorly conductive materials, such as solar cell silicon, and a semiconductor wafer manufacturing method and a solar battery cell manufacturing method based on the wire electric discharge machining method. Electrical discharge machining of a high volume resistivity, hard and brittle materials, having a volume resistivity that is equal to or higher than 0.5 ?·cm and equal to or lower than 5 ?·cm is performed by applying a pulse voltage having a pulse width that is equal to or higher than 1 ?sec and equal to or lower than 4 ?sec and having a peak current at the time of machining a wire electrode that is equal to or higher than 10A and equal to or lower than 50A to a wire electrode and generating a discharge pulse between the wire electrode and a subject to be machined.Type: GrantFiled: November 16, 2005Date of Patent: March 20, 2012Assignee: Mitsubishi Electric CorporationInventors: Tatsushi Sato, Yoshihito Imai, Teiji Takahashi, Takeshi Sakata, Tomoko Sendai, Yoichiro Nishimoto, Shigeru Matsuno, Takeyuki Maegawa, Takaaki Iwata
-
Patent number: 8106678Abstract: A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.Type: GrantFiled: December 23, 2009Date of Patent: January 31, 2012Assignee: Elpida Memory, Inc.Inventors: Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi
-
Patent number: 7978524Abstract: A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.Type: GrantFiled: August 24, 2010Date of Patent: July 12, 2011Assignee: Hitachi, Ltd.Inventors: Satoru Hanzawa, Takeshi Sakata
-
Patent number: 7969765Abstract: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.Type: GrantFiled: October 8, 2008Date of Patent: June 28, 2011Assignee: Elpida Memory, Inc.Inventors: Tomonori Sekiguchi, Shinichi Miyatake, Takeshi Sakata, Riichiro Takemura, Hiromasa Noda, Kazuhiko Kajigaya
-
Patent number: 7881088Abstract: The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.Type: GrantFiled: February 6, 2009Date of Patent: February 1, 2011Assignee: Elpida Memory, Inc.Inventors: Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya
-
Publication number: 20100315895Abstract: A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.Type: ApplicationFiled: August 24, 2010Publication date: December 16, 2010Inventors: Satoru HANZAWA, Takeshi Sakata
-
Publication number: 20100309741Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data.Type: ApplicationFiled: August 19, 2010Publication date: December 9, 2010Inventors: HIROYUKI MIZUNO, Takeshi Sakata, Nobuhiro Oodaira, Takao Watanabe, Yusuke Kanno