Patents by Inventor Takeshi Takagi
Takeshi Takagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9006793Abstract: A stacking structure in which a stacked body (21) including a first conductive layer (13), a semiconductor layer (17), and a second conductive layer (18) and an interlayer insulating film (16) are alternately stacked in parallel to a substrate, a plurality of columnar electrodes (12) arranged so as to penetrated through the stacking structure in a stacking direction, a variable resistance layer (14) which is disposed between the columnar electrode (12) and the first conductive layer (13) and which has a resistance value that reversibly changes according to an application of an electric signal are included. The variable resistance layer (14) is formed by oxidizing part of the first conductive layer (13). The variable resistance layer (14) and an insulating film for electrically separating the semiconductor layer (17) and the second conductive layer (18) from the columnar electrode (12) are simultaneously formed in a single oxidation process.Type: GrantFiled: June 29, 2011Date of Patent: April 14, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Zhiqiang Wei, Takeshi Takagi, Mitsuteru Iijima
-
Patent number: 9006698Abstract: A variable resistance element including: a first electrode; a second electrode; and a variable resistance layer having a resistance value which reversibly changes according to electrical signals applied, wherein the variable resistance layer includes a first variable resistance layer comprising a first oxygen-deficient transition metal oxide, and a second variable resistance layer comprising a second transition metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first oxygen-deficient transition metal oxide, the second electrode has a single needle-shaped part at an interface with the second variable resistance layer, and the second variable resistance layer is interposed between the first variable resistance layer and the second electrode, is in contact with the first variable resistance layer and the second electrode, and covers the single needle-shaped part.Type: GrantFiled: January 18, 2012Date of Patent: April 14, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Zhiqiang Wei, Takeshi Takagi, Satoru Mitani, Yoshio Kawashima, Ichirou Takahashi
-
Publication number: 20150083989Abstract: In accordance with an embodiment, a resistive random access memory device includes a substrate, first and second wiring lines, and a storage cell. The first and second wiring lines are disposed on the substrate so as to intersect each other. The storage cell is disposed between the first and second wiring lines at the intersection of the first and second wiring lines and includes a first electrode, a resistive switching film on the first electrode, a second electrode on the resistive switching film, and a tantalum oxide (TaOx) layer. The first electrode is electrically connected to the first wiring line. The second electrode is electrically connected to the second wiring line. The tantalum oxide (TaOx) layer is disposed between the first electrode and the resistive switching film and is in contact with the resistive switching film.Type: ApplicationFiled: August 29, 2014Publication date: March 26, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuki ODE, Takeshi Yamaguchi, Takeshi Takagi, Toshiharu Tanaka, Masaki Yamato
-
Patent number: 8969168Abstract: Provided is a method for manufacturing a variable resistance element, the method including: forming a first electrode material layer above a substrate; forming a first tantalum oxide material layer; forming a second tantalum oxide material layer; forming a second electrode material layer; and annealing at least the first tantalum oxide material layer after forming the first tantalum oxide material layer and before forming the second electrode material layer, wherein an oxygen content percentage of one of the first tantalum oxide material layer and the second tantalum oxide material layer is higher than an oxygen content percentage of the other.Type: GrantFiled: January 30, 2012Date of Patent: March 3, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Takeki Ninomiya, Yukio Hayakawa, Takumi Mikawa, Takeshi Takagi
-
Patent number: 8957399Abstract: A variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer including: a first oxide layer including a metal oxide having non-stoichiometric composition and including p-type carriers; a second oxide layer located between and in contact with the first oxide layer and a second electrode and including a metal oxide having non-stoichiometric composition and including n-type carriers; an oxygen reservoir region located in the first oxide layer, having no contact with the first electrode, and having an oxygen content atomic percentage higher than that of the first oxide layer; and a local region located in the second oxide layer, having contact with the oxygen reservoir region, and having an oxygen content atomic percentage lower than that of the second oxide layer.Type: GrantFiled: October 22, 2012Date of Patent: February 17, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Zhiqiang Wei, Takeshi Takagi, Koji Katayama
-
Patent number: 8939018Abstract: An analyzing device includes a feeder connected to a container in which a sample is contained for sucking the sample from the container and feeding the sample, and a controller for performing control for feeding from the feeder to a measurer. In measuring the sample, the controller performs control so that results of a plurality of times of measurement are obtained with respect to the single container in which the sample is contained, without changing the container. This arrangement allows quick accuracy check.Type: GrantFiled: October 2, 2009Date of Patent: January 27, 2015Assignee: ARKRAY, Inc.Inventors: Toshikatsu Sakai, Akira Sezaki, Takeshi Takagi
-
Patent number: 8942025Abstract: A variable resistance nonvolatile memory element writing method according to the present disclosure includes: (a) changing a variable resistance layer to a low resistance state by applying, to a second electrode, a first voltage which is negative with respect to a first electrode; and (b) changing the variable resistance layer to a high resistance state. Step (b) includes: (i) applying, to the second electrode, a second voltage which is positive with respect to the first electrode; and (ii) changing the variable resistance layer to the high resistance state by applying, to the second electrode, a third voltage, which is negative with respect to the first electrode and is smaller than the absolute value of a threshold voltage for changing the variable resistance layer from the high resistance state to the low resistance state, after the positive second voltage is applied in step (i).Type: GrantFiled: August 9, 2012Date of Patent: January 27, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Koji Katayama, Satoru Mitani, Takeshi Takagi
-
Publication number: 20140321197Abstract: In a driving method of a non-volatile memory element, the polarity of a write voltage pulse applied to change a variable resistance layer from a high-resistance state to a low-resistance state is such that an input/output terminal which is more distant from the variable resistance element becomes a source terminal, and when a first write voltage pulse is applied to change the variable resistance layer in the high-resistance state to the low-resistance state, a first gate voltage is applied to a gate terminal, while when a second write voltage pulse which is greater in absolute value of voltage than the first write voltage pulse is applied to change the variable resistance layer in an excess-resistance state to the low-resistance state, a second gate voltage which is smaller in absolute value than the first gate voltage is applied to the gate terminal.Type: ApplicationFiled: April 29, 2014Publication date: October 30, 2014Inventors: Takeki NINOMIYA, Koji KATAYAMA, Takeshi TAKAGI, Zhiqiang WEI
-
Patent number: 8854864Abstract: A nonvolatile memory element includes: a first electrode; a second electrode; and a variable resistance layer comprising a metal oxide positioned between the first electrode and the second electrode. The variable resistance layer includes: a first oxide layer having a resistivity ?x, on the first electrode; a second oxide layer having a resistivity ?y (?x<?y), on the first oxide layer; a third oxide layer having a resistivity ?z (?y<?z), on the second oxide layer; and a localized region that is positioned in the third oxide layer and the second oxide layer to be in contact with the second electrode and not to be in contact with the first oxide layer, and is, in resistivity, lower than the third oxide layer and different from the second oxide layer.Type: GrantFiled: November 8, 2012Date of Patent: October 7, 2014Assignee: Panasonic CorporationInventors: Zhiqiang Wei, Takeki Ninomiya, Takeshi Takagi
-
Publication number: 20140278160Abstract: An estimation method for a variable resistance element including (i) a first electrode, (ii) a second electrode, and therebetween (iii) a variable resistance layer in which a local region is formed which has resistive status that reversibly changes according to an electric pulse applied between the first electrode and the second electrode, the estimation method including: obtaining, when changes are made to the resistive status of the local region, measurement values each indicating a resistance state after one of the changes; and determining, based on a distribution of the obtained measurement values, an estimated amount of a physical parameter regarding structural characteristics of the local region by a calculation.Type: ApplicationFiled: March 18, 2014Publication date: September 18, 2014Applicant: Panasonic CorporationInventors: Zhiqiang WEI, Takeki NINOMIYA, Shunsaku MURAOKA, Takeshi TAKAGI
-
Patent number: 8830730Abstract: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate, (ii) a variable resistance element having: lower and upper electrodes; and a variable resistance layer whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes, and (iii) a MOS transistor formed on the substrate, wherein the variable resistance layer includes: oxygen-deficient transition metal oxide layers having compositions MOx and MOy (where x<y) and in contact with the electrodes respectively, a diffusion layer region is connected with the lower electrode to form a memory cell, the region serving as a drain upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer.Type: GrantFiled: September 6, 2013Date of Patent: September 9, 2014Assignee: Panasonic CorporationInventors: Shunsaku Muraoka, Yoshihiko Kanzawa, Satoru Mitani, Koji Katayama, Kazuhiko Shimakawa, Satoru Fujii, Takeshi Takagi
-
Patent number: 8822972Abstract: A non-volatile memory element including a first electrode; a second electrode; and a variable resistance layer. The variable resistance layer including, when a first metal is M and a second metal is N: a third metal oxide layer NOz; a second metal oxide layer NOy; and a first metal oxide layer MOx such that the third, second and first metal oxide layers are stacked in this order; wherein when an oxygen content atomic percentage of an oxide of the first metal M in a stoichiometric state is A, an oxygen content atomic percentage of an oxide of the second metal N in a stoichiometric state is B, an oxygen content atomic percentage of MOx is C, an oxygen content atomic percentage of NOy is D, and an oxygen content atomic percentage of NOz is E, (D/B)<(C/A), (E/B)<(C/A) and y<z are satisfied.Type: GrantFiled: September 26, 2013Date of Patent: September 2, 2014Assignee: Panasonic CorporationInventors: Ryutaro Yasuhara, Takeki Ninomiya, Takeshi Takagi
-
Patent number: 8796660Abstract: A nonvolatile memory element (20) of the present invention comprises a resistance variable element (14) and a diode (18) which are formed on a substrate (10) such that the resistance variable element (14) has a resistance variable layer (11) sandwiched between a lower electrode (12) and an upper electrode (13), and the diode (18) which is connected in series with the resistance variable element (14) in the laminating direction and has an insulating layer or semiconductor layer (15) sandwiched between a first electrode (16) at the lower side and a second electrode (17) at the upper side. The resistance variable layer (11) is embedded in a first contact hole (21) formed on the lower electrode (12).Type: GrantFiled: September 21, 2007Date of Patent: August 5, 2014Assignee: Panasonic CorporationInventors: Takeshi Takagi, Takumi Mikawa
-
Publication number: 20140203234Abstract: A variable resistance nonvolatile memory element includes: first and second electrode layers; a first variable resistance layer between the first and second electrode layers; and a second variable resistance layer between the second electrode layer and the first variable resistance layer and having a higher resistance value than the first variable resistance layer. When viewed in a direction perpendicular to the major surface of the second variable resistance layer, an outline of the second variable resistance layer is located inwardly of the outline of any one of the second electrode layer and the first variable resistance layer, and an outline of a face of the second variable resistance layer, the face being in contact with the first variable resistance layer is located inwardly of an outline of a face of the first variable resistance layer, the face being in contact with the second variable resistance layer.Type: ApplicationFiled: January 18, 2013Publication date: July 24, 2014Applicant: Panasonic CorporationInventors: Takeki Ninomiya, Takeshi Takagi, Koji Katayama, Yoshio Kawashima
-
Publication number: 20140126268Abstract: A method of driving a nonvolatile memory element including a variable resistance element having a state reversibly changing between low and high resistance states by an applied electrical signal and a transistor serially connected to the variable resistance element. The method including: setting the variable resistance element to the low resistance state by applying a first gate voltage to a gate of the transistor and applying a first write voltage negative with respect to a first electrode; and changing a resistance value of the transistor obtained in a low-resistance write operation, when a value of current passing through the variable resistance element in the setting of the low resistance state or a resistance value of the nonvolatile memory element in the case where the variable resistance element is in the low resistance state is outside a predetermined range.Type: ApplicationFiled: April 17, 2013Publication date: May 8, 2014Applicant: Panasonic CorporationInventors: Koji Katayama, Satoru Mitani, Shunsaku Muraoka, Zhiqiang Wei, Takeshi Takagi
-
Publication number: 20140117305Abstract: A non-volatile memory element including a first electrode; a second electrode; and a variable resistance layer. The variable resistance layer including, when a first metal is M and a second metal is N, a third metal oxide layer NOz; a second metal oxide layer NOy; and a first metal oxide layer MOx such that the third, second and first metal oxide layers are stacked in this order; wherein when an oxygen content atomic percentage of an oxide of the first metal M in a stoichiometric state is A, an oxygen content atomic percentage of an oxide of the second metal N in a stoichiometric state is B, an oxygen content atomic percentage of MOx is C, an oxygen content atomic percentage of NOy is D, and an oxygen content atomic percentage of NOz is E, (D/B)<(C/A), (E/B)<(C/A) and y<z are satisfied.Type: ApplicationFiled: September 26, 2013Publication date: May 1, 2014Applicant: PANASONIC CORPORATIONInventors: Ryutaro YASUHARA, Takeki NINOMIYA, Takeshi TAKAGI
-
Patent number: 8710484Abstract: A manufacturing method for manufacturing, with a simple process, a non-volatile memory apparatus having a stable memory performance includes: (a) forming a stacking-structure body above a substrate by alternately stacking conductive layers comprising a transition metal and interlayer insulating films comprising an insulating material; (b) forming a contact hole penetrating through the stacking-structure body to expose part of each of the conductive layers; (c) forming variable resistance layers by oxidizing the part of each of the conductive layers, the part being exposed in the contact hole, and each of the variable resistance layers having a resistance value that reversibly changes according to an application of an electric signal; and (d) forming a pillar electrode in the contact hole by embedding a conductive material in the contact hole, the pillar electrode being connected to each of the variable resistance layers.Type: GrantFiled: February 23, 2011Date of Patent: April 29, 2014Assignee: Panasonic CorporationInventors: Zhiqiang Wei, Takeshi Takagi, Mitsuteru Iijima
-
Patent number: 8712702Abstract: A measuring apparatus for measuring a predetermined physical property of a liquid measuring sample comprises a preparing unit in which a plurality of materials including at least a liquid material are mixed; a supply route which supplies the liquid material to the preparing unit; a withdrawing unit which withdraws the measuring sample from the preparing unit into the supply route, the measuring sample being prepared to contain the liquid material supplied to the preparing unit via the supply route; and a measuring unit which measures the predetermined physical property of the measuring sample withdrawn into the supply route by the withdrawing unit.Type: GrantFiled: June 23, 2011Date of Patent: April 29, 2014Assignee: ARKRAY, Inc.Inventors: Takeshi Takagi, Koji Okumura, Tatsuo Kamata
-
Patent number: 8686390Abstract: Provided is a nonvolatile memory element achieving a stable resistance change and miniaturization, and a method of manufacturing the same. The nonvolatile memory element includes: a first electrode formed above a substrate; an interlayer insulating layer formed above the substrate including the first electrode and having a memory cell hole reaching the first electrode; a barrier layer formed in the memory cell hole and composed of a semiconductor layer or an insulating layer connected to the first electrode; a second electrode formed in the memory cell hole and connected to the barrier layer; a variable resistance layer formed on the second electrode and having a stacked structure whose resistance value changes based on electric signals; and a third electrode connected to the variable resistance layer and formed on the interlayer insulating layer to cover the memory cell hole.Type: GrantFiled: November 18, 2010Date of Patent: April 1, 2014Assignee: Panasonic CorporationInventor: Takeshi Takagi
-
Patent number: 8675393Abstract: Provided is a method for driving a non-volatile memory element in which a variable resistance element including a first electrode, a second electrode, and a variable resistance layer capable of reversibly changing between a high resistance state and a low resistance state with application of electrical signals having different polarities is connected in series with a current steering element having bidirectional rectifying characteristics with respect to an applied voltage. After the non-volatile memory element is manufactured, the resistance value of the variable resistance layer is reduced from a resistance value in the initial resistance state higher than that in the high resistance state by applying, to the non-volatile memory element, a voltage pulse having the polarity identical to that of the voltage pulse for changing the variable resistance layer from the low resistance state to the high resistance state in the normal operations.Type: GrantFiled: March 18, 2011Date of Patent: March 18, 2014Assignee: Panasonic CorporationInventors: Koji Katayama, Takeshi Takagi, Mitsuteru Iijima