Abstract: This invention provides a switching power supply control circuit based on the parallel operation scheme that suppresses ripples in the output voltage. The control circuit comprises switching circuit blocks 10 and 20 connected in parallel, output reactors 31 and 32 connected in parallel corresponding to the switching circuit blocks 10 and 20, and a control circuit 40 that controls the operation of the switching circuit blocks 10 and 20.

Abstract: This invention provides a switching power supply control circuit that can switch the output voltage with high precision and at high speed. The control circuit comprises an A/D converter 31 that generates a output voltage digital value D1 indicating the actual output Vo in response to clock signal CLK1, a reference voltage generating circuit 32 that generates a reference voltage digital value D2 that indicated the target value of the output voltage in response to clock signal CLK2, a subtracter 33 that compares the output voltage digital value D1 and reference voltage digital value D2 and generates an error voltage digital value D3 based thereupon, a latch circuit 34 that reads the error voltage digital value D3 in response to clock signal CLK3 and controls the operation of the switching circuit block 10 based thereupon and an arithmetic circuit 35.

Abstract: A switching power supply which can obtain high accuracy of the output voltage without increasing the clock frequency is disclosed. A switching power supply according to the present invention employs an output detector for detecting an output voltage Vo of the switching power supply and a signal generator for generating a switching control signal SW based on the output voltage Vo of the switching power supply. The switching control signal SW includes during each control period Tc a plurality of pulses each having either a first pulse width or a second pulse width different from the first pulse width. According to the present invention, the accuracy of the output voltage Vo can in effect be enhanced by controlling the number of the pulses having the second pulse width in each control period.

Abstract: Disclosed is a virtual channel memory access controlling circuit for controlling accesses from a plurality of memory masters to a virtual channel memory having a plurality of channels, comprising: a channel information storing portion having a plurality of storage areas, each of the storage areas being assigned to any of the memory masters, each of the storage areas corresponding to each of the channels, each of the storage areas having a channel number and a memory address, the channel number identifying a channel, and the memory address being sent to the virtual channel memory; detector for detecting necessity of a change of assignment of storage area between memory masters; and changer for dynamically changing the assignment of the storage area between memory masters.

Abstract: Disclosed is a virtual channel memory access controlling circuit for controlling accesses from a plurality of memory masters to a virtual channel memory having a plurality of channels, comprising: a channel information storing portion having a plurality of storage areas, each of the storage areas being assigned to any of the memory masters, each of the storage areas corresponding to each of the channels, each of the storage areas having a channel number and a memory address, the channel number identifying a channel, and the memory address being sent to the virtual channel memory; detector for detecting necessity of a change of assignment of storage area between memory masters; and changer for dynamically changing the assignment of the storage area between memory masters.

Abstract: A flicker reducing circuit that can prevent a degradation of an image by performing an outline blur correction together with a flicker reduction. In the flicker reducing circuit, a vertical contour detecting circuit detects an outline of the vertical component of a horizontal straight line. A switch selects an addition signal from the vertical low-pass filter for a period during which it is judged that an outline corresponds to the vertical component of a horizontal straight line according to the detection signal. The addition signal is obtained by adding the low-frequency component of a spatial frequency in a vertical direction to an output signal from the differentiating circuit. During other periods, the switch selects a delay display signal not subjected to a filtering process, output from the delaying circuit.

Abstract: A digital integrated circuit incorporates a plurality of multi-port flip-flop circuits which are interconnected by a plurality of gate circuits. A separate source of clock pulses is provided for each of the ports of the multi-port flip-flop circuits, and each clock pulse source is selectively effective to cause the multi-port flip-flop circuits to perform independent functions. During operation under one source of clock pulses, the flip-flops perform their ordinary function as D type flip-flops. During operation under another source of clock pulses, the flip-flops function as one or more shift registers in order to set the flip-flops to a predefined initial state in accordance with serial input data, and/or to provide serial output data in response to the state of the flip-flops following a preceding operation.