Patents by Inventor Takeshi Yamaguchi

Takeshi Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170373119
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate extending in a first direction and a second direction, the first and second directions intersecting each other; a first wiring line disposed above the semiconductor substrate and extending in the first direction; a second wiring line disposed above the semiconductor substrate and extending in a third direction, the third direction intersecting the first direction and the second direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a first insulating film disposed aligned with the second wiring line in the first direction; a first film disposed between the first wiring line and the first insulating film; and a second film disposed between the first insulating film and the first film and configured from a material different from that of the first film.
    Type: Application
    Filed: March 21, 2017
    Publication date: December 28, 2017
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi OGA, Mutsumi OKAJIMA, Natsuki FUKUDA, Takeshi YAMAGUCHI, Toshiharu TANAKA, Hiroyuki ODE
  • Publication number: 20170355119
    Abstract: Provided is a screw that is for use in an injection molding machine and that makes it possible to benefit from the kneading effect of a multi-start screw while minimizing the received friction resistance. The screw for an injection molding machine is provided with a first stage 20 on the upstream side and a second stage 30 on the downstream side. The screw for an injection molding machine is characterized in that: the first stage 20 is provided with a compression section 22 comprising a main scraper 25 and an auxiliary scraper 26 having a smaller outer diameter than the main scraper 25; and the second stage 30 is provided with a multi-start screw section 31, said multi-start screw section being provided on the upstream side and comprising a plurality of scrapers, and a fin kneading section 32 provided downstream from the multi-start screw section.
    Type: Application
    Filed: January 15, 2015
    Publication date: December 14, 2017
    Inventors: Munehiro NOBUTA, Naoki TODA, Toshihiko KARIYA, Takeshi YAMAGUCHI, Kiyoshi KINOSHITA
  • Publication number: 20170319086
    Abstract: A blood circuit having a pressure measurement portion connected to a pressure measurement device includes: a first measurement portion provided downstream of a pumping segment; and a second measurement portion provided upstream of the pumping segment. The first measurement portion includes: a first housing having a tubular shape; and a first flexible membrane having a tubular shape and provided in the first housing. The second measurement portion includes: a second housing having a tubular shape; and a second flexible membrane having a tubular shape and provided in the second housing. A space between the first flexible membrane and the first housing is larger than a space between the second flexible membrane and the second housing in an initial state before permitting the blood to flow.
    Type: Application
    Filed: October 28, 2015
    Publication date: November 9, 2017
    Applicant: NIPRO CORPORATION
    Inventors: Toshiaki MASUDA, Takeshi YAMAGUCHI
  • Patent number: 9812887
    Abstract: A secondary-battery monitoring device capable of realizing highly reliable overcurrent detection and a battery pack having it are provided. When an overcurrent flowing to a secondary battery is to be detected by utilizing a current detection voltage generated via on-resistance of a discharge-control switch and a charge-control switch, a voltage correction circuit that generates a correction voltage having a characteristic varied by positive slope or negative slope along with increase in a power supply voltage is provided, and the correction voltage is added to the detection voltage or a reference power supply voltage with the polarity that cancels out the slope of voltage variation caused in the detection voltage, and then the voltage is input to a comparator circuit. In this manner, variation in the overcurrent determination current is reduced.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: November 7, 2017
    Assignee: MITSUMI ELECTRIC CO., LTD.
    Inventors: Shogo Nagata, Yasuaki So, Takeshi Yamaguchi, Norihito Kawaguchi
  • Publication number: 20170312954
    Abstract: Provided is an injection molding method for resin that contains reinforcing fiber, the method being capable of easily eliminating uneven distribution of added components. The injection molding method is provided with: a plasticizing step for supplying resin pellets P and added components to a cylinder equipped with a screw 10, which has a rotating axis as the center is capable of rotating normally and in reverse, and generating molten resin by rotating the screw 10 in the normal direction; and an injecting step for injecting the molten resin M comprising the added components into a cavity. In the plasticizing step, a reverse rotation operation for reversing the rotation of the screw 10 is performed or a screw-stopping operation of stopping the normal rotation of the screw 10 is performed with a prescribed timing and for a prescribed period.
    Type: Application
    Filed: June 25, 2015
    Publication date: November 2, 2017
    Inventors: Munehiro NOBUTA, Naoki TODA, Toshihiko KARIYA, Takeshi YAMAGUCHI, Kiyoshi KINOSHITA
  • Publication number: 20170308222
    Abstract: An electronic apparatus includes a display unit that displays information, a capacitive touch panel layer that transmits display of the display unit, and detects coordinates indicated by an indicator separated from a surface in a predetermined distance, a glass that protects the touch panel layer, and transmits the display of the display unit, a pressure sensor that detects distortion of the glass, and a control unit that validates and invalidates the coordinates detected by the touch panel layer. The control unit validates the coordinates detected by the touch panel layer in a case where the indicator is an active pen, and validates the coordinates most recently detected by the touch panel layer, when a predetermined amount of distortion is detected by the pressure sensor, in a case where the indicator is other than an active pen.
    Type: Application
    Filed: November 17, 2016
    Publication date: October 26, 2017
    Inventors: Tomoki TAKANO, Takeshi YAMAGUCHI
  • Publication number: 20170310854
    Abstract: An image forming apparatus includes a printing unit, an in-line colorimeter and an in-line scanner. A hardware processor is configured to control the printing unit, the in-line colorimeter and the in-line scanner, to perform the following operations. The hardware processor uses the printing unit to print a first color chart to be measured with the in-line scanner and an external colorimeter, and a second color chart to be measured with the in-line scanner and the in-line colorimeter. A hardware processor creates a scanner profile based on RGB values and colorimetric values of patches of the second size in the second area in the first color chart, and uses RGB values and colorimetric values of patches of the first size in the first area in each of the first and second color charts, to calculates correction amounts for use in estimation of colorimetric values by using the scanner profile.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 26, 2017
    Applicant: KONICA MINOLTA, INC.
    Inventor: Takeshi YAMAGUCHI
  • Publication number: 20170308208
    Abstract: An electronic device includes a housing, a display that displays predetermined information, an electrostatic-capacitance touch panel that allows visible light corresponding to display contents of the display to pass through the touch panel, a transparent member that protects the touch panel and that allows the visible light to pass through the transparent member, and a detector that detects deformation of the transparent member. The touch panel detects a pair of two-dimensional coordinates indicated by an indicator, wherein when the touch panel detects a plurality of pairs of two-dimensional coordinates and when the detector detects a predetermined deformation amount; at least one pair of two-dimensional coordinates detected during a predetermined time period prior to a time when the deformation is detected is validated.
    Type: Application
    Filed: July 12, 2017
    Publication date: October 26, 2017
    Applicant: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Tomoki TAKANO, Takeshi YAMAGUCHI, Yuuichi TAKIZAWA
  • Patent number: 9779809
    Abstract: A semiconductor memory device includes a control circuit configured to apply a first voltage to a selected first line, apply a second voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively. The control circuit includes a detection circuit configured to detect a transition of a resistance state of a selected memory cell using a reference voltage. The control circuit is configured to execute a read operation in which the control circuit applies the third voltage to the selected first line and the non-selected first line, applies the second voltage to the selected second line, and applies the fourth voltage to the non-selected second line, and set the reference voltage based on a voltage value of the selected second line.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: October 3, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shigeki Kobayashi, Takeshi Yamaguchi
  • Patent number: 9768233
    Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body facing the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a lower surface of the projecting part contacting an upper surface of the one of the first conductive films.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: September 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Natsuki Fukuda, Mutsumi Okajima, Atsushi Oga, Toshiharu Tanaka, Takeshi Yamaguchi, Takeshi Takagi, Masanori Komura
  • Publication number: 20170256588
    Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body facing the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a lower surface of the projecting part contacting an upper surface of the one of the first conductive films.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 7, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Natsuki FUKUDA, Mutsumi OKAJIMA, Atsushi OGA, Toshiharu TANAKA, Takeshi YAMAGUCHI, Takeshi TAKAGI, Masanori KOMURA
  • Patent number: 9755442
    Abstract: A battery protection IC has detection circuits to detect faults of an overcharge, an over-discharge, and an overcurrent of a secondary battery; a control circuit to protect the secondary battery, by controlling (dis)charging the secondary battery upon the fault; and a delay circuit to generate delay after the fault before the controlling. The IC includes a memory unit to store data for setting and adjusting a circuit characteristic of the IC; and a setting circuit to set and adjust the circuit characteristic, based on the data from the memory unit. The memory unit includes a pair of non-volatile memory cells to complementarily store one bit, and a latch circuit directly cross-coupled with the memory cells, for each bit of the data. The latch circuit statically outputs the data from the memory cells to the setting circuit when the IC is turned on.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: September 5, 2017
    Assignee: MITSUMI ELECTRIC CO., LTD.
    Inventors: Ryota Kageyama, Tsutomu Yamauchi, Nobuhito Tanaka, Takashi Takeda, Yoshihiro Satake, Takeshi Yamaguchi, Koji Koshimizu, Norihito Kawaguchi
  • Publication number: 20170228098
    Abstract: A touch panel has a first zone, a second zone and a third zone. The first zone includes a first vertical distance, which is less than a first value and greater than a second value, from the surface of the display, and includes a center of the display. The second zone includes the first vertical distance and is located outside the first zone with respect to the two dimensional coordinates. The third zone includes a second vertical distance, which is greater than the first value, from the surface of the display. When the indicator directly enters the second zone from the third zone, the two dimensional coordinates of the indicator are invalid. The two dimensional coordinates of the indicator are valid coordinates, when the indicator directly enters the second zone from the third zone, or when the indicator directly enters the first zone from the third zone.
    Type: Application
    Filed: March 6, 2017
    Publication date: August 10, 2017
    Applicant: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Tomoki TAKANO, Takeshi YAMAGUCHI
  • Patent number: 9728585
    Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor substrate which extends in first and second directions that intersect each other; a plurality of first wiring lines which are arranged in a third direction that intersects the first direction and the second direction, and which extend in the first direction; a plurality of second wiring lines which are arranged in the first direction and extend in the third direction; and a plurality of memory cells disposed at intersections of the first wiring lines and the second wiring lines, one of the memory cells having a first film whose resistance changes electrically, a thickness in the second direction of the first film changing with respect to a change of position in the third direction, and the first films of two of the memory cells adjacent in the third direction being separated between the two memory cells.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: August 8, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaki Yamato, Takeshi Yamaguchi, Takeshi Takagi, Natsuki Fukuda
  • Patent number: 9727197
    Abstract: An electronic device includes a housing, a display, an electrostatic-capacitance touch panel, a transparent member that protects the touch panel, and a depression detector. The touch panel is configured to detect a pair of two-dimensional coordinates indicated by an indicator having predetermined conductivity, wherein when the touch panel detects a plurality of pairs of two-dimensional coordinates and when the depression detector detects a predetermined amount of deformation, at least one pair of two-dimensional coordinates detected during a predetermined time period prior to a time when the deformation is detected is validated; and a pair of two-dimensional coordinates detected before the predetermined time period prior to the time when the deformation is detected, is not validated, wherein the predetermined time period does not include a deformation of an amount equal to or greater than the predetermined amount of deformation.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: August 8, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Tomoki Takano, Takeshi Yamaguchi, Yuuichi Takizawa
  • Patent number: 9721961
    Abstract: In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mutsumi Okajima, Atsushi Oga, Takeshi Yamaguchi, Hiroyuki Ode, Toshiharu Tanaka, Natsuki Fukuda
  • Patent number: 9711721
    Abstract: According to one embodiment, a plurality of first wirings are disposed in a first direction and a second direction which intersect with each other, and extended in a third direction. A second wiring stack is configured to include second wirings and interlayer insulating films which are extended and alternately stacked in the second direction. A memory cell includes, in the first direction, a first variable resistive layer which is disposed on a side near the first wiring and a second variable resistive layer which is disposed on a side near the second wiring. The second variable resistive layer is disposed between the interlayer insulating films in the third direction, and made of a material which is obtained by oxidizing the second wiring.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: July 18, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Takagi, Takeshi Yamaguchi
  • Patent number: 9704922
    Abstract: According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: July 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Oga, Mutsumi Okajima, Takeshi Yamaguchi, Hiroyuki Ode, Toshiharu Tanaka, Natsuki Fukuda
  • Patent number: 9679947
    Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: June 13, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaki Yamato, Yasuhiro Nojiri, Shigeki Kobayashi, Hiroyuki Fukumizu, Takeshi Yamaguchi
  • Patent number: 9669573
    Abstract: The injection molding apparatus of the present invention includes: a heating cylinder; a screw that is provided rotatably in an inner portion of the heating cylinder; a resin feed hopper that feeds a resin pellet; and a fiber feed device that is provided ahead of the resin feed hopper and feeds reinforcing fibers into the heating cylinder. The screw includes a first stage that is located on a rear side, and in which the resin pellet is melted, and a second stage that is located on a front side, and in which the melted resin pellet and the reinforcing fibers are mixed, and a lead of a second flight provided in the second stage is larger than a lead of a first flight provided in the first stage.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: June 6, 2017
    Assignee: MITSUBISHI HEAVY INDUSTRIES PLASTIC TECHNOLOGY CO., LTD.
    Inventors: Toshihiko Kariya, Naoki Toda, Munehiro Nobuta, Kiyoshi Kinoshita, Takeshi Yamaguchi, Kosuke Ikeda, Yuji Suzumura, Hitoshi Onuma, Ryoji Okabe, Masanori Takahashi