Patents by Inventor Takeshi Yamaguchi

Takeshi Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180269318
    Abstract: A power semiconductor device of the present invention includes: a semiconductor base body which has a super junction structure formed of a plurality of first conductive-type columnar regions and a plurality of second conductive-type columnar regions; a plurality of trenches; gate insulation films; gate electrodes; an interlayer insulation film; contact holes formed such that two or more contact holes are formed between two trenches disposed adjacently to each other; metal plugs formed by filling the inside of the contact holes with metal; and an electrode, wherein a first conductive-type high concentration diffusion region is formed only between the trench and the metal plug disposed closest to the trench between each two trenches disposed adjacently to each other. According to the power semiconductor device of the present invention, it is possible to provide a power semiconductor device which satisfies a demand for reduction in cost and downsizing of electronic equipment, and has a large breakdown strength.
    Type: Application
    Filed: January 16, 2017
    Publication date: September 20, 2018
    Inventors: Mizue KITADA, Takeshi ASADA, Takeshi YAMAGUCHI, Noriaki SUZUKI, Daisuke ARAI
  • Publication number: 20180258592
    Abstract: An all-purpose type tissue paper. A two-ply tissue paper that does not have moisturizer applied thereon, that has a basis weight per ply of 10.0-16.0 g/m2, a paper thickness per two-ply of 120-200 ?m, a softness of not more than 1.0, a dry tensile strength (T) in the MD direction of 240-300 cN/25 mm, and an average dynamic friction coefficient of 1.40-1.65.
    Type: Application
    Filed: August 4, 2016
    Publication date: September 13, 2018
    Applicants: DAIO PAPER CORPORATION, TOHOKU UNIVERSITY
    Inventors: Shuta YASUI, Norimitsu HIRATA, Hidenori YOROZU, Kazuo HOKKIRIGAWA, Takeshi YAMAGUCHI, Kei SHIBATA, Wataru TANABE, Shohei MATSUMURA
  • Patent number: 10074694
    Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the first direction and a resistance change film provided between the first wiring and the second wiring. The second wiring includes a first conductive layer and a first intermediate layer including a first region provided between the first conductive layer and the resistance change film. The first intermediate layer includes a material having nonlinear resistance characteristics.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: September 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Takagi, Takeshi Yamaguchi, Masaki Yamato, Hiroyuki Ode, Toshiharu Tanaka
  • Publication number: 20180249027
    Abstract: A control unit includes a touch panel display capable of presenting preview display of multiple pages of document images in a scrollable manner on the display panel. The touch panel display controller includes: a commanded position detecting controller that detects a commanded position relative to one of document images being a reference in the preview image displayed on a display panel; a preview layout direction switching controller that switches the layout direction in the preview image in accordance with the commanded position; and a scroll direction switching controller that switches the scrolling direction in the preview image in accordance with the detected commanded position.
    Type: Application
    Filed: April 27, 2018
    Publication date: August 30, 2018
    Inventor: Takeshi YAMAGUCHI
  • Publication number: 20180233213
    Abstract: According to one embodiment, a semiconductor circuit includes a plurality of memories. The memories are connected to one another in series such that an output node of the memory of the first stage is connected to an input node of the memory of the second stage. The semiconductor circuit includes a test circuit that outputs test data to an input node of the memory of the first stage among the plurality of memories, and a comparison circuit that compares data output from an output node of the memory of the final stage among the plurality of memories with expectation value data.
    Type: Application
    Filed: August 30, 2017
    Publication date: August 16, 2018
    Inventors: Tsutomu MIYAMAE, Nariyuki FUKUDA, Kazuhito HOSAKA, Takeshi YAMAGUCHI, Suguru TAHARA, Isao OOIGAWA, Keitarou MISHIMA, Yuichiro SANUKI
  • Publication number: 20180233257
    Abstract: A novel wire harness protection structure and a method for producing a braided cover-equipped wire harness that can prevent interference between the braided cover and other members without increasing the number of extra steps after braiding. The wire harness protection structure that protects an outer circumferential surface of a wire harness by using a braided cover, including a fold-back portion provided on one end side in an axial direction of the braided cover, the fold-back portion being formed by folding back a terminal end processed portion provided at a braiding start end, inward in a radial direction of the braided cover.
    Type: Application
    Filed: February 9, 2018
    Publication date: August 16, 2018
    Inventor: Takeshi YAMAGUCHI
  • Patent number: 10013129
    Abstract: An electronic device includes a housing, a display that displays predetermined information, an electrostatic-capacitance touch panel that allows visible light corresponding to display contents of the display to pass through the touch panel, a transparent member that protects the touch panel and that allows the visible light to pass through the transparent member, and a detector that detects deformation of the transparent member. The touch panel detects a pair of two-dimensional coordinates indicated by an indicator, wherein when the touch panel detects a plurality of pairs of two-dimensional coordinates and when the detector detects a predetermined deformation amount; at least one pair of two-dimensional coordinates detected during a predetermined time period prior to a time when the deformation is detected is validated.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: July 3, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Tomoki Takano, Takeshi Yamaguchi, Yuuichi Takizawa
  • Patent number: 10001880
    Abstract: A strain quantity threshold value is set in accordance with a distance from a pressure detection unit for each divided predetermined subdivision which is obtained by dividing an operation surface of a touch panel unit into a plurality of subdivisions. The minimum value of the strain quantity threshold value is set to be a value larger than a strain quantity when water or the like is attached to the operation surface of the touch panel unit.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: June 19, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takeshi Yamaguchi, Tomoki Takano
  • Patent number: 9986112
    Abstract: A control unit includes a touch panel display capable of presenting preview display of multiple pages of document images in a scrollable manner on the display panel. The touch panel display controller includes: a commanded position detecting controller that detects a commanded position relative to one of document images being a reference in the preview image displayed on a display panel; a preview layout direction switching controller that switches the layout direction in the preview image in accordance with the commanded position; and a scroll direction switching controller that switches the scrolling direction in the preview image in accordance with the detected commanded position.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: May 29, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Takeshi Yamaguchi
  • Patent number: 9979860
    Abstract: An image forming apparatus includes a printing unit, an in-line colorimeter and an in-line scanner. A hardware processor is configured to control the printing unit, the in-line colorimeter and the in-line scanner, to perform the following operations. The hardware processor uses the printing unit to print a first color chart to be measured with the in-line scanner and an external colorimeter, and a second color chart to be measured with the in-line scanner and the in-line colorimeter. A hardware processor creates a scanner profile based on RGB values and colorimetric values of patches of the second size in the second area in the first color chart, and uses RGB values and colorimetric values of patches of the first size in the first area in each of the first and second color charts, to calculates correction amounts for use in estimation of colorimetric values by using the scanner profile.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 22, 2018
    Assignee: KONICA MINOLTA, INC.
    Inventor: Takeshi Yamaguchi
  • Patent number: 9971447
    Abstract: An electronic apparatus includes a display unit that displays information, a capacitive touch panel layer that transmits display of the display unit, and detects coordinates indicated by an indicator separated from a surface in a predetermined distance, a glass that protects the touch panel layer, and transmits the display of the display unit, a pressure sensor that detects distortion of the glass, and a control unit that validates and invalidates the coordinates detected by the touch panel layer. The control unit validates the coordinates detected by the touch panel layer in a case where the indicator is an active pen, and validates the coordinates most recently detected by the touch panel layer, when a predetermined amount of distortion is detected by the pressure sensor, in a case where the indicator is other than an active pen.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: May 15, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tomoki Takano, Takeshi Yamaguchi
  • Publication number: 20180090214
    Abstract: A semiconductor integrated circuit includes a first circuit, a second circuit, a memory circuit having a plurality of flip-flops, a storage unit, a signal generating unit to produce an operation mode setting signal, a control circuit configured to cause the memory circuit to operate such that the plurality of flip-flops holds a value for setting characteristics of the first circuit when the operation mode setting signal indicates a first operation mode, and configured to cause the memory circuit to operate as a counter to measure a time length used in the second circuit when the operation mode setting signal indicates a second operation mode, and a setting circuit configured to cause trimming data stored in the storage unit to set the characteristic of the first circuit when the operation mode setting signal indicates the second operation mode, the trimming data corresponding to the value held by the memory circuit.
    Type: Application
    Filed: September 13, 2017
    Publication date: March 29, 2018
    Applicant: MITSUMI ELECTRIC CO., LTD.
    Inventor: Takeshi YAMAGUCHI
  • Patent number: 9926221
    Abstract: To provide a near infrared cutoff filter glass which is excellent in optical properties such that the transmittance of visible light is high, and the transmittance of near infrared light is low. A near infrared cutoff filter glass comprising components of P, F, Al, R (R is at least one member selected from Li, Na and K), R? (R? is at least one member selected from Mg, Ca, Sr, Ba and Zn) and Cu, wherein (Cu+/the total amount of Cu)×100[%] is within a range of from 0.01 to 4.0%.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 27, 2018
    Assignee: Asahi Glass Company, Limited
    Inventors: Makoto Shiratori, Takeshi Yamaguchi
  • Publication number: 20180076264
    Abstract: A semiconductor memory device according to an embodiment includes: a first wiring line extending in a first direction; a second wiring line extending in a second direction, the second direction intersecting the first direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a channel body disposed at a first end of the first wiring line; a third wiring line electrically connected to the first wiring line via the channel body; and a gate wiring line extending in the first direction and facing the channel body from the second direction.
    Type: Application
    Filed: March 21, 2017
    Publication date: March 15, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takahiko SASAKI, Takeshi YAMAGUCHI
  • Patent number: 9905759
    Abstract: According to one embodiment, a memory device includes a pillar, a first wiring, a second wiring, an insulating film provided between the first wiring and the second wiring, a first layer provided between the first wiring and the pillar in the second direction and including a first metal oxide containing a first metal and oxygen, a second layer provided between the second wiring and the pillar in the second direction and including the first metal oxide containing the first metal and oxygen, and an intermediate film provided between the pillar and the first layer and between the pillar and the second layer in the second direction and including a second metal oxide containing the first metal and oxygen. Concentration of oxygen contained in the first metal oxide is lower than concentration of oxygen contained in the second metal oxide.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: February 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Takagi, Takeshi Yamaguchi, Masaki Yamato, Hiroyuki Ode, Toshiharu Tanaka
  • Publication number: 20180037492
    Abstract: A near-infrared cut filter glass includes: P, Al, R (R represents any one or more of Li, Na, and K), R? (R? represents any one or more of Mg, Ca, Sr, Ba, and Zn), and Cu, and not including F practically, wherein (Cu+ amount/total Cu amount)×100[%] is 0.01 to 7.0%. The filter glass may further include, by mol %, 0 to 10% B2O3. The filter glass may have a fracture toughness value of the near-infrared cut filter glass is 0.3 MPa·m1/2 or more. For the filter glass, a quotient obtained by dividing an absorption constant at a wavelength of 430 nm by an absorption constant at a wavelength of 800 nm, of the near-infrared cut filter glass, may be 0.00001 to 0.19.
    Type: Application
    Filed: October 17, 2017
    Publication date: February 8, 2018
    Applicant: ASAHI GLASS COMPANY, LIMITED
    Inventors: Takahiro SAKAGAMI, Takeshi YAMAGUCHI, Makoto SHIRATORI
  • Patent number: 9880679
    Abstract: An electronic apparatus includes a display unit that displays predetermined information and an electrostatic capacitive touch panel unit through which display of the display unit passes and that determines a two-dimensional coordinate indicated by an instructing object which has some conductivity. In the electronic apparatus, when a predetermined condition is satisfied, a two-dimensional coordinate corresponding to the instructing object is caused to be effective and the effective two-dimensional coordinate is changed depending on movement of the instructing object, and when the effective two-dimensional coordinate is changed in a predetermined range for a predetermined time, the effective two-dimensional coordinate is caused to be ineffective.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: January 30, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takeshi Yamaguchi, Tomoki Takano
  • Publication number: 20180022003
    Abstract: Provided is an injection molding method in which a constricting section is provided at a boundary between a first stage and a second stage of a screw. When a mixture of a molten resin and reinforcing fibers passes through the constricting section, compression force higher than compression force on an upstream side of the constricting section is applied to the mixture. A supply section on a downstream side of the constricting section has a shaft diameter smaller than an outer diameter of the constricting section. Therefore, the vicinity of the supply section becomes a reduced-pressure region with respect to the mixture having passed through the constricting section, and the mixture is accordingly expanded. As a result, spring-back occurs on the reinforcing fibers and a Barus effect occurs on the molten resin, thereby making it possible to produce a state that is advantageous to open the fiber bundle.
    Type: Application
    Filed: January 16, 2015
    Publication date: January 25, 2018
    Inventors: Munehiro NOBUTA, Naoki TODA, Toshihiko KARIYA, Takeshi YAMAGUCHI, Kiyoshi KINOSHITA
  • Publication number: 20180013926
    Abstract: A color conversion apparatus includes a hardware processor that obtains a scanner profile created on the basis of measured RGB values and corresponding measured colorimetric values of patches in a first color chart, and creates a table including correction amounts of RGB values, each according to the level of flare estimated for a patch and each associated with an RGB-value difference and a patch-size difference, on the basis of RGB values of patches in the first color chart and RGB values of patches in a specific chart. The specific chart is created by using a part of the patches in the first color chart with the RGB value or patch size being changed. The hardware processor further corrects measured RGB values of patches in a second color chart with the table, and convers the corrected RGB values into colorimetric values with the scanner profile.
    Type: Application
    Filed: July 6, 2017
    Publication date: January 11, 2018
    Applicant: Konica Minolta, Inc.
    Inventor: Takeshi Yamaguchi
  • Publication number: 20180013061
    Abstract: According to one embodiment, a memory device includes a stacked body. The stacked body includes first and second electrodes, and an oxide layer provided between the first and second electrodes. The second electrode includes a semiconductor layer, and a metal-containing region including at least one of first or second metallic element and being provided between at least a portion of the semiconductor layer and at least a portion of the oxide layer. The first metallic element includes at least one selected from Pt, Pd, Ir, Ru, Re, and Os. The second metallic element includes at least one selected Ti, W, Mo, and Ta. The stacked body has first and second states. The first state is obtained by causing a current to flow in the stacked body from the second toward first electrode. The second state is obtained by causing a current to flow from the first toward second electrode.
    Type: Application
    Filed: July 7, 2017
    Publication date: January 11, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Hiroyuki FUKUMIZU, Takeshi YAMAGUCHI