Patents by Inventor Takeyoshi Masuda
Takeyoshi Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9659773Abstract: A method for manufacturing a SiC semiconductor device includes the steps of: forming an impurity region in a SiC layer; forming a first carbon layer on a surface of the SiC layer having the impurity region formed therein, by selectively removing silicon from the surface; forming a second carbon layer on the first carbon layer; and heating the SiC layer having the first carbon layer and the second carbon layer formed therein.Type: GrantFiled: August 11, 2014Date of Patent: May 23, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventor: Takeyoshi Masuda
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Patent number: 9647081Abstract: A method for manufacturing a silicon carbide semiconductor device includes steps of preparing a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, forming a groove portion in the first main surface of the silicon carbide substrate, and cutting the silicon carbide substrate at the groove portion. The step of forming the groove portion includes a step of thermally etching the silicon carbide substrate using chlorine. Thereby, a method for manufacturing a silicon carbide semiconductor device capable of suppressing damage to a chip is provided.Type: GrantFiled: July 9, 2014Date of Patent: May 9, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Wada, Takeyoshi Masuda, Mitsuhiko Sakai
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Patent number: 9647072Abstract: A silicon carbide semiconductor device has a silicon carbide substrate, a gate insulating film, and a gate electrode. Silicon carbide substrate includes a first impurity region having a first conductivity type, a well region being in contact with the first impurity region and having a second conductivity type which is different from the first conductivity type, and a second impurity region separated from the first impurity region by the well region and having the first conductivity type. The gate insulating film is in contact with the first impurity region and the well region. The gate electrode is in contact with the gate insulating film and is arranged opposite to the well region with respect to the gate insulating film. A specific on-resistance at a voltage which is half a gate driving voltage applied to the gate electrode is smaller than twice the specific on-resistance at the gate driving voltage.Type: GrantFiled: November 6, 2013Date of Patent: May 9, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada, Takashi Tsuno
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Patent number: 9647106Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, a gate electrode, an interlayer insulating film, and a gate interconnection. The silicon carbide substrate includes: a first impurity region; a second impurity region provided on the first impurity region; and a third impurity region provided on the second impurity region so as to be separated from the first impurity region. A trench has a side portion and a bottom portion, the side portion extending to the first impurity region through the third impurity region and the second impurity region, the bottom portion being located in the first impurity region. When viewed in across section, the interlayer insulating film extends from above the third impurity region to above the gate electrode so as to cover the corner portion.Type: GrantFiled: January 16, 2015Date of Patent: May 9, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventor: Takeyoshi Masuda
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Publication number: 20170117381Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes: a substrate having a main surface; and a silicon carbide layer formed on the main surface of the substrate and including a side surface inclined relative to the main surface. The side surface substantially includes a {03-3-8} plane. The side surface includes a channel region.Type: ApplicationFiled: January 5, 2017Publication date: April 27, 2017Inventors: Takeyoshi Masuda, Shin Harada, Misako Honaga, Keiji Wada, Toru Hiyoshi
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Patent number: 9627488Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided.Type: GrantFiled: July 14, 2016Date of Patent: April 18, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Toru Hiyoshi, Kosuke Uchida, Takeyoshi Masuda
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Patent number: 9627525Abstract: Provided is a silicon carbide semiconductor device that enables integration of a transistor element and a Schottky barrier diode while avoiding the reduction of an active region. A silicon carbide semiconductor device includes a silicon carbide layer, a gate insulating film, a Schottky electrode being Schottky functioned to a drift layer via a first contact hole and an opening, a gate electrode being arranged on the gate insulating film, an insulating layer being arranged so as to cover the gate insulating film, the gate electrode, and the Schottky electrode and having a second contact hole for exposing the gate electrode, and a gate pad electrode being arranged on the insulating layer so as to overlap the Schottky electrode in a plan view and being electrically connected to the gate electrode via the second contact hole.Type: GrantFiled: July 28, 2014Date of Patent: April 18, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Toru Hiyoshi, Keiji Wada, Takeyoshi Masuda
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Patent number: 9627487Abstract: A silicon carbide substrate has first to third semiconductor layers. The first and third semiconductor layers have a first conductivity type, and the second semiconductor layer has a second conductivity type. A trench has a bottom surface and first to third side surfaces, the bottom surface being constituted of the first semiconductor layer, the first to third side surfaces being respectively constituted of the first to third semiconductor layers. A gate insulating film having a bottom portion and a side wall portion is provided on the trench. The bottom portion has a minimum thickness d0. A portion of the side wall portion on the second side surface has a minimum thickness d1. A portion, connected to the bottom portion, of the side wall portion on the first side surface has a thickness d2. Moreover, d2>d1 and d2>d0 are satisfied.Type: GrantFiled: March 5, 2014Date of Patent: April 18, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kenji Hiratsuka, Yu Saitoh, Takeyoshi Masuda
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Patent number: 9583346Abstract: A method for manufacturing a silicon carbide semiconductor device includes steps below. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface having a maximal diameter greater than 100 mm, is prepared. An impurity region is formed on a side of the first main surface of the silicon carbide substrate. In a plan view, a cover member is arranged on the side of the first main surface so as to cover at least the entire impurity region. The silicon carbide substrate is annealed at a temperature lower than a melting point of the cover member while the cover member is arranged on the side of the first main surface of the silicon carbide substrate.Type: GrantFiled: September 24, 2014Date of Patent: February 28, 2017Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shunsuke Yamada, Takeyoshi Masuda, Taku Horii
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Publication number: 20170047415Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate oxide film, and a gate electrode. A trench is provided in the main surface to have a side surface and a bottom portion. A contact point between a first side surface portion and a second side surface portion is located in a third impurity region. An angle formed by the first side surface portion and a straight line extending through the contact point and parallel to the main surface is smaller than an angle formed by the second side surface portion and a boundary surface between a first impurity region and a second impurity region. A thickness of a portion of the gate oxide film on the contact point between the main surface and the first side surface portion is larger than a thickness of a portion of the gate oxide film on the second impurity region.Type: ApplicationFiled: April 9, 2015Publication date: February 16, 2017Inventors: Yu Saitoh, Tomoaki Hatayama, Takeyoshi Masuda
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Patent number: 9570543Abstract: A semiconductor substrate has an element portion and a termination portion located on an outer side of the element portion. A first electrode layer is provided on a first surface of the semiconductor substrate. A second electrode layer is provided on a second surface of the semiconductor substrate in an upper portion of the element portion. An interlayer insulation film is provided on the second surface of the semiconductor substrate. The interlayer insulation film has: an element insulation portion that provides insulation between a part of the element portion of the semiconductor substrate and the second electrode layer; and a termination insulation portion covering a termination portion of the semiconductor substrate. The termination insulation portion includes a high dielectric constant film that is higher in dielectric constant than the element insulation portion.Type: GrantFiled: April 14, 2014Date of Patent: February 14, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takeyoshi Masuda, Shunsuke Yamada
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Patent number: 9543412Abstract: A silicon carbide substrate including a first layer having first conductivity type, a second layer having second conductivity type, and a third layer having the first conductivity type is formed. A trench provided with an inner surface having a side wall surface and a bottom surface is formed, the side wall surface extending through the third layer and the second layer and reaching the first layer, the bottom surface being formed of the first layer. A silicon film is formed to cover the bottom surface. A gate oxide film is formed on the inner surface by oxidation in the trench. The gate oxide film includes a first portion formed by oxidation of the silicon carbide substrate, and a second portion formed by oxidation of the silicon film on the bottom surface. Accordingly, a method for manufacturing a silicon carbide semiconductor device having a high breakdown voltage is provided.Type: GrantFiled: June 16, 2015Date of Patent: January 10, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hideki Hayashi, Takeyoshi Masuda
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Patent number: 9543429Abstract: There is provided a silicon carbide semiconductor device allowing for increased switching speed with a simpler configuration. A silicon carbide semiconductor device includes: a gate electrode provided on a gate insulating film; and a gate pad. The gate electrode includes a first comb-tooth shaped electrode portion extending from outside of the gate pad toward a circumferential edge portion of the gate pad and overlapping with the gate pad at the circumferential edge portion of the gate pad when viewed in a plan view. A p+ region includes: a central portion overlapping with the gate pad when viewed in the plan view; and a peripheral portion extending from the central portion toward the outside of the gate pad, the peripheral portion being provided to face the first comb-tooth shaped electrode portion of the gate electrode with a space interposed therebetween.Type: GrantFiled: August 11, 2014Date of Patent: January 10, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada
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Patent number: 9490319Abstract: The trench has, in a cross-sectional view, a first corner portion which is an intersection between a first sidewall surface and a bottom portion and a second corner portion which is an intersection between a second sidewall surface and the bottom portion. A first layer has a second-conductivity-type region. In a cross-sectional view, the second-conductivity-type region is arranged to intersect with a line which passes through any of the first corner portion and the second corner portion and is in parallel to a <0001> direction of a silicon carbide crystal forming the silicon carbide layer. A ratio calculated by dividing SP by ST is not lower than 20% and not higher than 130%, where ST represents a total area of the trenches in a boundary surface between the first layer and a second layer and SP represents a total area of the second-conductivity-type regions in a plan view.Type: GrantFiled: February 4, 2014Date of Patent: November 8, 2016Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Wada, Yu Saitoh, Takeyoshi Masuda
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Publication number: 20160322465Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided.Type: ApplicationFiled: July 14, 2016Publication date: November 3, 2016Inventors: Toru Hiyoshi, Kosuke Uchida, Takeyoshi Masuda
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Publication number: 20160300943Abstract: There is provided a silicon carbide semiconductor device allowing for increased switching speed with a simpler configuration. A silicon carbide semiconductor device includes: a gate electrode provided on a gate insulating film; and a gate pad. The gate electrode includes a first comb-tooth shaped electrode portion extending from outside of the gate pad toward a circumferential edge portion of the gate pad and overlapping with the gate pad at the circumferential 1edge portion of the gate pad when viewed in a plan view. A p+ region includes: a central portion overlapping with the gate pad when viewed in the plan view; and a peripheral portion extending from the central portion toward the outside of the gate pad, the peripheral portion being provided to face the first comb-tooth shaped electrode portion of the gate electrode with a space interposed therebetween.Type: ApplicationFiled: August 11, 2014Publication date: October 13, 2016Inventors: Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada
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Publication number: 20160293423Abstract: A method for manufacturing a silicon carbide semiconductor device includes steps below. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface having a maximal diameter greater than 100 mm, is prepared. An impurity region is formed on a side of the first main surface of the silicon carbide substrate. In a plan view, a cover member is arranged on the side of the first main surface so as to cover at least the entire impurity region. The silicon carbide substrate is annealed at a temperature lower than a melting point of the cover member while the cover member is arranged on the side of the first main surface of the silicon carbide substrate.Type: ApplicationFiled: September 24, 2014Publication date: October 6, 2016Inventors: Shunsuke YAMADA, Takeyoshi MASUDA, Taku HORII
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Publication number: 20160293690Abstract: A silicon carbide film has first and second main surfaces. The second main surface has an element formation surface and a termination surface. The silicon carbide film has a first range that constitutes a first main surface and an intermediate surface opposite to the first main surface, and a second range that is provided on the intermediate surface and constitutes the element formation surface. The first range includes: a first breakdown voltage holding layer, and a guard ring region partially provided at the intermediate surface in the termination portion. The second range has a second breakdown voltage holding layer. The second range has one of a structure only having the second breakdown voltage holding layer in the termination portion and a structure disposed only in the element portion of the element portion and the termination portion.Type: ApplicationFiled: November 27, 2013Publication date: October 6, 2016Inventors: Takeyoshi MASUDA, Keiji WADA
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Publication number: 20160293708Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The gate insulating film is provided as being in contact with the first main surface of the silicon carbide substrate. The gate electrode is provided on the gate insulating film such that the gate insulating film lies between the gate electrode and the silicon carbide substrate. In a first stress test in which a gate voltage of ?5 V is applied to the gate electrode for 100 hours at a temperature of 175° C., an absolute value of a difference between a first threshold voltage and a second threshold voltage is not more than 0.5 V, with a threshold voltage before the first stress test being defined as the first threshold voltage and a threshold voltage after the first stress test being defined as the second threshold voltage.Type: ApplicationFiled: September 18, 2014Publication date: October 6, 2016Applicants: Sumitomo Electric Industries, Ltd., Renesas Electronics CorporationInventors: Ryosuke Kubota, Shunsuke Yamada, Taku Horii, Takeyoshi Masuda, Daisuke Hamajima, So Tanaka, Shinji Kimura, Masayuki Kobayashi
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Patent number: 9443960Abstract: An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region.Type: GrantFiled: March 10, 2015Date of Patent: September 13, 2016Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takeyoshi Masuda, Keiji Wada, Toru Hiyoshi