Patents by Inventor Taku MAEKAWA

Taku MAEKAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Signal processing system, signal processing circuit, and reset control method
    Patent number: 11360529
    Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: June 14, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi Ueda, Ryoji Hashimoto, Taku Maekawa, Katsushige Matsubara, Keisuke Matsumoto
  • Signal processing system, signal processing circuit, and reset control method
    Patent number: 10725512
    Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi Ueda, Ryoji Hashimoto, Taku Maekawa, Katsushige Matsubara, Keisuke Matsumoto
  • SIGNAL PROCESSING SYSTEM, SIGNAL PROCESSING CIRCUIT, AND RESET CONTROL METHOD
    Publication number: 20200233471
    Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.
    Type: Application
    Filed: April 7, 2020
    Publication date: July 23, 2020
    Inventors: Hiroshi UEDA, Ryoji HASHIMOTO, Taku MAEKAWA, Katsushige MATSUBARA, Keisuke MATSUMOTO
  • SIGNAL PROCESSING SYSTEM, SIGNAL PROCESSING CIRCUIT, AND RESET CONTROL METHOD
    Publication number: 20180253127
    Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.
    Type: Application
    Filed: December 29, 2017
    Publication date: September 6, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Hiroshi UEDA, Ryoji HASHIMOTO, Taku MAEKAWA, Katsushige MATSUBARA, Keisuke MATSUMOTO