Patents by Inventor Taku Shibaguchi

Taku Shibaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210288174
    Abstract: A semiconductor device includes a first well of a first conductivity type formed to extend inwardly from a first region on one surface of the semiconductor substrate; a second well of a second conductivity type formed to extend inwardly from a second region separated from the first region on said surface of the semiconductor substrate; a third well of the first conductivity type formed to extend inwardly from a third region separated from the second region on said surface of the semiconductor substrate; and a conductive layer formed over the first region, the second region, and the third region on said surface of the semiconductor substrate. A recess is formed to expose a side face of the first well, and the conductive layer is formed to cover a top surface of the first well exposed in the first region and at least part of the side face.
    Type: Application
    Filed: March 10, 2021
    Publication date: September 16, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Taku SHIBAGUCHI
  • Patent number: 11031408
    Abstract: A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell disposed on the semiconductor substrate. The nonvolatile memory cell includes a field-effect transistor for data writing, and a field-effect transistor for data readout that is adjacent to the field-effect transistor for data writing. Each of the field-effect transistor for data writing and the field-effect transistor for data readout includes a gate insulating film formed on the semiconductor substrate, a floating gate formed on the gate insulating film, and diffusion layers configuring a source region and a drain region on respective sides of the floating gate viewed in the thickness direction of the semiconductor substrate. The thickness of the gate insulating film of the field-effect transistor for data readout, and the thickness of the gate insulating film of the field-effect transistor for data writing, are different.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 8, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Taku Shibaguchi
  • Publication number: 20200312860
    Abstract: A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell disposed on the semiconductor substrate. The nonvolatile memory cell includes a field-effect transistor for data writing, and a field-effect transistor for data readout that is adjacent to the field-effect transistor for data writing. Each of the field-effect transistor for data writing and the field-effect transistor for data readout includes a gate insulating film formed on the semiconductor substrate, a floating gate formed on the gate insulating film, and diffusion layers configuring a source region and a drain region on respective sides of the floating gate viewed in the thickness direction of the semiconductor substrate. The thickness of the gate insulating film of the field-effect transistor for data readout, and the thickness of the gate insulating film of the field-effect transistor for data writing, are different.
    Type: Application
    Filed: February 27, 2020
    Publication date: October 1, 2020
    Inventor: TAKU SHIBAGUCHI
  • Publication number: 20120132984
    Abstract: A contact plug 40 electrically connected to an impurity diffusion region between sidewalls of an adjacent pair of memory cells 1 is provided to pass through an interlayer dielectric film 18. A side wall of a contact hole 41 is covered with a sealing film 42 denser than the interlayer dielectric film 18. The contact plug 40 includes a barrier metal film 43 formed to cover a surface of the sealing film 42 and a bottom surface portion of the contact hole 41 and a metal plug 44 embedded in the contact hole 41 in a state surrounded by the barrier metal film 43.
    Type: Application
    Filed: February 2, 2012
    Publication date: May 31, 2012
    Applicant: ROHM CO., LTD.
    Inventors: Michihiko Mifuji, Yuichi Nakao, Toshikazu Mizukoshi, Bungo Tanaka, Taku Shibaguchi, Gentaro Morikawa