Abstract: In a method of manufacturing a semiconductor device of an embodiment, first and second mask patterns are formed on a stacked body formed on a semiconductor substrate. Then, a first step-like pattern and a first dummy pattern are formed from the stacked body. When the second mask pattern becomes smaller than a predetermined size, a resist is applied, and a third mask pattern using the resist is formed. Then, a second step-like pattern and a second dummy pattern are formed from the stacked body.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, memory cell component layers, a dividing part, and a complementary film. The memory cell component layers are provided on the semiconductor layer such that memory cells are arranged in a three-dimensional state. The dividing part extends from an upper surface of the memory cell component layers to a predetermined depth of the semiconductor layer. The dividing part includes a first spacer film made of an insulating material and provided on a side in contact with the memory cell component layers, and a filling film embedded in a region surrounded by the first spacer film. The complementary film is made of a conductive material and provided between the filling film and the semiconductor layer.

Abstract: A method of manufacturing a semiconductor device includes forming a stack of films including a conductive film layer above a semiconductor substrate; patterning the stack of films by dry etching; and cleaning including generation of plasma in an ambient including BCl3 and controlling a bias power to a nonbiased state.

Abstract: A semiconductor device according to the embodiment includes a first stack structure. The first stack structure includes at least one first insulating film and a plurality of first conducting films above a surface of a substrate. A link portion electrically connects the first conducting films in the first stack structure. A second stack structure includes a plurality of second insulating films and a plurality of second conducting films on the first stack structure. A semiconductor pillar passes through the second stack structure to reach the first stack structure and is insulated from the first and second stack structures.

Abstract: A method of manufacturing a semiconductor device includes forming a stack of films including a conductive film layer above a semiconductor substrate; patterning the stack of films by dry etching; and cleaning including generation of plasma in an ambient including BCl3 and controlling a bias power to a nonbiased state.

Abstract: According to one embodiment, a second electrode layer is formed on first structures where a first electrode layer and a first memory cell layer sequentially stacked above a substrate are patterned in a line-and-space shape extending in a first direction and a first interlayer insulating film embedded between the first structures. Etching is performed from the second electrode layer to a predetermined position in an inner portion of the first memory cell layer by using a first mask layer having a line-and-space pattern extending in a second direction, so that a first trench is formed. A first modifying film is formed on a side surface of the first trench, anisotropic etching is performed on the first memory cell layer by using the first mask layer, and after that, isotropic etching is performed.

Abstract: An embodiment includes: a stacked body having an impurity doped silicon layer and an interlayer insulating film alternately stacked on each other in which one layer of the impurity doped silicon layers is replaced with a conductive film enabling forming a metal oxide; a hole penetrating the stacked body in a stacking direction; a channel layer formed in the hole along the stacking direction of the stacked body; a tunnel insulating film formed between an inner surface of the hole and the channel layer; a charge trapping layer formed between the inner surface of the hole and the tunnel insulating film; and a block insulating film formed between the inner surface of the hole and the charge trapping layer.

Abstract: According to one embodiment, a memory cell section includes a memory layer in which a non-volatile memory cell is arranged at an intersecting position of a first wiring and a second wiring to be sandwiched by the first wiring and the second wiring. A first drawing section connects the memory cell section and a first contact section with the first wiring, and a second drawing section connects the memory cell section and a second contact section with the second wiring. A dummy pattern is provided in a layer corresponding to the memory layer immediately below the first and second wirings configuring the first and second drawing sections.

Abstract: A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the floating gate with the inclusion of the second insulating film; an element isolation insulating film formed in the semiconductor substrate and extending in a gate-length direction to isolate between memory cells adjoining in a gate-width direction; and an air gap formed on the element isolation insulating film and between floating gates adjoining in the gate-width direction.

Abstract: According to one embodiment, a non-volatile memory device is formed as described below. First, a wiring material layer, which configures a part of a wiring of an element, is stacked above an element layer, the wiring material layer is processed in a predetermined shape, and the element layer is etched using the wiring material layer as a mask. Next, an insulation layer is embedded between etched patterns, and the insulation layer is removed using the wiring material layer as a stopper. Then, a wiring layer, which is in contact with the wiring material layer, is formed on the insulation layer from which the wiring material layer is exposed.

Abstract: According to one embodiment, a second electrode layer is formed on first structures where a first electrode layer and a first memory cell layer sequentially stacked above a substrate are patterned in a line-and-space shape extending in a first direction and a first interlayer insulating film embedded between the first structures. Etching is performed from the second electrode layer to a predetermined position in an inner portion of the first memory cell layer by using a first mask layer having a line-and-space pattern extending in a second direction, so that a first trench is formed. A first modifying film is formed on a side surface of the first trench, anisotropic etching is performed on the first memory cell layer by using the first mask layer, and after that, isotropic etching is performed.

Abstract: According to one embodiment, a memory cell section includes a memory layer in which a non-volatile memory cell is arranged at an intersecting position of a first wiring and a second wiring to be sandwiched by the first wiring and the second wiring. A first drawing section connects the memory cell section and a first contact section with the first wiring, and a second drawing section connects the memory cell section and a second contact section with the second wiring. A dummy pattern is provided in a layer corresponding to the memory layer immediately below the first and second wirings configuring the first and second drawing sections.

Abstract: A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the floating gate with the inclusion of the second insulating film; an element isolation insulating film formed in the semiconductor substrate and extending in a gate-length direction to isolate between memory cells adjoining in a gate-width direction; and an air gap formed on the element isolation insulating film and between floating gates adjoining in the gate-width direction.

Abstract: According to one embodiment, a method for manufacturing an integrated circuit device, includes etching a metal member using a gas including a halogen, forming a silicon oxide film so as to cover an etching face of the etched metal member without exposing the metal member to atmospheric air, and removing the silicon oxide film.

Abstract: A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.

Abstract: According to one embodiment, a method is described for manufacturing a semiconductor device. The method can form a conductive layer including tungsten on a foundation layer. The method can form a trench by selectively etching the conductive layer. The trench is shallower than a depth from a surface of the conductive layer to the foundation layer. The method can form a protective film on a side surface and a bottom surface of the conductive layer in the trench using a gas containing bromine. The protective film includes a compound of the tungsten and the bromine. The method can remove the protective film on the bottom surface of the conductive layer. The method can etch a portion of the conductive layer below the trench with the protective film on the side surface of the conductive layer.

Abstract: A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the floating gate with the inclusion of the second insulating film; an element isolation insulating film formed in the semiconductor substrate and extending in a gate-length direction to isolate between memory cells adjoining in a gate-width direction; and an air gap formed on the element isolation insulating film and between floating gates adjoining in the gate-width direction.

Abstract: According to one embodiment, a non-volatile memory device is formed as described below. First, a wiring material layer, which configures a part of a wiring of an element, is stacked above an element layer, the wiring material layer is processed in a predetermined shape, and the element layer is etched using the wiring material layer as a mask. Next, an insulation layer is embedded between etched patterns, and the insulation layer is removed using the wiring material layer as a stopper. Then, a wiring layer, which is in contact with the wiring material layer, is formed on the insulation layer from which the wiring material layer is exposed.

Abstract: According to one embodiment, a method is described for manufacturing a semiconductor device. The method can form a conductive layer including tungsten on a foundation layer. The method can form a trench by selectively etching the conductive layer. The trench is shallower than a depth from a surface of the conductive layer to the foundation layer. The method can form a protective film on a side surface and a bottom surface of the conductive layer in the trench using a gas containing bromine. The protective film includes a compound of the tungsten and the bromine. The method can remove the protective film on the bottom surface of the conductive layer. The method can etch a portion of the conductive layer below the trench with the protective film on the side surface of the conductive layer.

Abstract: A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the floating gate with the inclusion of the second insulating film; an element isolation insulating film formed in the semiconductor substrate and extending in a gate-length direction to isolate between memory cells adjoining in a gate-width direction; and an air gap formed on the element isolation insulating film and between floating gates adjoining in the gate-width direction.