Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array; a first insulating layer; and a passivation film. The memory cell array includes first interconnect layers and a first memory pillar. The first interconnect layers extend in a first direction substantially parallel to a semiconductor substrate. The first memory pillar passes through the first interconnect layers and extends in a second direction substantially perpendicular to the semiconductor substrate. The first insulating layer is provided above the memory cell array. The passivation film is provided on the first insulating layer, and includes a protrusion at least above the memory cell array and between the passivation film and the first insulating layer.

Abstract: An information processing apparatus has an acquisitor configured to acquire an entire area image obtained by capturing an entire area of a processing surface of a wafer including at least one defect, a training image selector configured to select, as a training image, a partial image including at least one defect from the entire area image, a model constructor configured to construct a calculation model of generating a label image obtained by extracting and binarizing the defect included in the partial image, and a learner configured to update a parameter of the calculation model based on a difference between the label image generated by inputting the training image to the calculation model and a reference label image obtained by extracting and binarizing the defect of the training image.

Abstract: A semiconductor image processing apparatus has an image input unit inputs a first semiconductor image, an exposure condition input unit configured to input exposure conditions, a generator performs a process of extracting a feature amount in consideration of the exposure conditions while reducing resolution of the first semiconductor image and thereafter use the extracted feature amount to increase the resolution to generate a second semiconductor image, and a discriminator configured to discriminate whether the input image is the second semiconductor image or a third semiconductor image provided in advance. The generator performs learning so that the discriminator erroneously discriminates the second semiconductor image as the third semiconductor image based on a result discriminated by the discriminator.

Abstract: An information processing apparatus has an acquisitor configured to acquire an entire area image obtained by capturing an entire area of a processing surface of a wafer including at least one defect, a training image selector configured to select, as a training image, a partial image including at least one defect from the entire area image, a model constructor configured to construct a calculation model of generating a label image obtained by extracting and binarizing the defect included in the partial image, and a learner configured to update a parameter of the calculation model based on a difference between the label image generated by inputting the training image to the calculation model and a reference label image obtained by extracting and binarizing the defect of the training image.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array; a first insulating layer; and a passivation film. The memory cell array includes first interconnect layers and a first memory pillar. The first interconnect layers extend in a first direction substantially parallel to a semiconductor substrate. The first memory pillar passes through the first interconnect layers and extends in a second direction substantially perpendicular to the semiconductor substrate. The first insulating layer is provided above the memory cell array. The passivation film is provided on the first insulating layer, and includes a protrusion at least above the memory cell array and between the passivation film and the first insulating layer.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array; a first insulating layer; and a passivation film. The memory cell array includes first interconnect layers and a first memory pillar. The first interconnect layers extend in a first direction substantially parallel to a semiconductor substrate. The first memory pillar passes through the first interconnect layers and extends in a second direction substantially perpendicular to the semiconductor substrate. The first insulating layer is provided above the memory cell array. The passivation film is provided on the first insulating layer, and includes a protrusion at least above the memory cell array and between the passivation film and the first insulating layer.

Abstract: A semiconductor image processing apparatus has an image input unit inputs a first semiconductor image, an exposure condition input unit configured to input exposure conditions, a generator performs a process of extracting a feature amount in consideration of the exposure conditions while reducing resolution of the first semiconductor image and thereafter use the extracted feature amount to increase the resolution to generate a second semiconductor image, and a discriminator configured to discriminate whether the input image is the second semiconductor image or a third semiconductor image provided in advance. The generator performs learning so that the discriminator erroneously discriminates the second semiconductor image as the third semiconductor image based on a result discriminated by the discriminator.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array; a first insulating layer; and a passivation film. The memory cell array includes first interconnect layers and a first memory pillar. The first interconnect layers extend in a first direction substantially parallel to a semiconductor substrate. The first memory pillar passes through the first interconnect layers and extends in a second direction substantially perpendicular to the semiconductor substrate. The first insulating layer is provided above the memory cell array. The passivation film is provided on the first insulating layer, and includes a protrusion at least above the memory cell array and between the passivation film and the first insulating layer.