Patents by Inventor Takumi Danjo

Takumi Danjo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220172117
    Abstract: A deep learning method is performed by a computer having a plurality of nodes. The method comprises measuring, in learning performed by using the plurality of nodes in deep learning, performance of each of the nodes, allocating a number of batches to be processed by an entirety of the plurality of nodes to the individual nodes in accordance with the respective performance measured, and processing the allocated batches in each of the nodes.
    Type: Application
    Filed: September 3, 2021
    Publication date: June 2, 2022
    Applicant: FUJITSU LIMITED
    Inventor: Takumi DANJO
  • Publication number: 20220147872
    Abstract: A non-transitory computer-readable recording medium storing a calculation processing program for causing a computer to execute processing, the processing including: calculating error gradients of a plurality of layers of a machine learning model that includes an input layer of the machine learning model at the time of machine learning of the machine learning model; selecting a layer of which the error gradient is less than a threshold as a suppression target of the machine learning; and controlling a learning rate and performing the machine learning on the layer selected as the suppression target in a certain period of time before the machine learning is suppressed.
    Type: Application
    Filed: August 30, 2021
    Publication date: May 12, 2022
    Applicant: FUJITSU LIMITED
    Inventors: YUTAKA KAI, Akihiko Kasagi, Yasushi Hara, Takumi Danjo
  • Publication number: 20220147772
    Abstract: A computer-implemented method includes: calculating error gradients with respect to a plurality of layers included in a machine learning model at a time of machine learning of the machine learning model, the plurality of layers including an input layer of the machine learning model; specifying, as a layer to be suppressed, a layer located in a range from a position of the input layer to a predetermined position among the layers in which the error gradient is less than a threshold; and suppressing the machine learning for the layer to be suppressed.
    Type: Application
    Filed: July 15, 2021
    Publication date: May 12, 2022
    Applicant: FUJITSU LIMITED
    Inventors: YUTAKA KAI, Akihiko Kasagi, Yasushi Hara, Takumi Danjo
  • Patent number: 11297127
    Abstract: An information processing system includes: a first information processing device that transmits first data to be retained via a communication path; a second information processing device that calculates first calculation result data that is a calculation result of the first data received via the communication path and second data to be retained and transmits the calculated first calculation result data via the communication path; a third information processing device that transmits third data to be retained via the communication path; and a fourth information processing device that calculates second calculation result data that is a calculation result of the third data received via the communication path and fourth data to be retained and calculates third calculation result data that is a calculation result of the first calculation result data received via the communication path and the calculated second calculation result data.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: April 5, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Takumi Danjo, Takashi Arakawa, Masakatsu Ito
  • Publication number: 20210397948
    Abstract: A memory holds a model including a plurality of layers including their respective parameters and training data. A processor starts learning processing, which repeatedly calculates an error of an output of the model by using the training data, calculates an error gradient, which indicates a gradient of the error with respect to the parameters, for each of the layers, and updates the parameters based on the error gradients. The processor calculates a difference between a first error gradient calculated in a first iteration in the learning processing and a second error gradient calculated in a second iteration after the first iteration for a first layer among the plurality of layers. In a case where the difference is less than a threshold, the processor skips the calculating of the error gradient and the updating of the parameter for the first layer in a third iteration after the second iteration.
    Type: Application
    Filed: March 10, 2021
    Publication date: December 23, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Yasushi Hara, Akihiko Kasagi, Takumi Danjo, YUTAKA KAI
  • Publication number: 20210312328
    Abstract: A non-transitory computer-readable storage medium storing a program that causes a processor included in a computer to execute a process, the process includes executing, in learning processing that is repeatedly executed for a model having a plurality of layers, update processing of a value of a parameter for at least one update suppression layer among the plurality of layers just once every k times (k is an integer of 2 or more) of the learning processing; and calculating, when the update processing of the value of the parameter for the update suppression layer is executed, a first value of the parameter after the update by a gradient descent method to which a momentum method is applied, by using a second of the parameter calculated in the learning processing k times before and a third value of the parameter calculated in the learning processing 2 k times before.
    Type: Application
    Filed: February 5, 2021
    Publication date: October 7, 2021
    Applicant: FUJITSU LIMITED
    Inventor: Takumi Danjo
  • Patent number: 11074493
    Abstract: Boltzmann machine includes a plurality of circuit units each having an adder that adds weighted input signals and a comparison unit that compares an output signal of the adder with a threshold signal to output a binary output signal; and digital arithmetic units each generating the weighted input signals by weighting the binary output signal of the circuit units with a weight. The comparison unit has a first comparator that compares a thermal noise with a reference voltage to output a binary digital random signal, a DA converter that converts the digital random signal to an analog random signal and varies a magnitude of the analog random signal, and a second comparator that compares the output signal of the adder with the analog random signal to generate the binary output signal with a predetermined probability function.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: July 27, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Takumi Danjo, Sanroku Tsukamoto, Hirotaka Tamura
  • Publication number: 20200371750
    Abstract: An arithmetic processing apparatus includes: a plurality of nodes (N nodes) capable of communicating with each other, each of the plurality of nodes including a memory and a processor, the memory being configured to store a value and an operation result, the processor being configured to execute first processing when N is a natural number of 2 or more, n is a natural number of 1 or more, and N?2n, wherein the first processing is configured to divide by 2 a value held by a first node, the first node being any of the plurality of nodes and a last node in an order of counting, obtain one or more node pairs by pairing remaining nodes among the plurality of nodes exception for the first node, and calculate repeatedly an average value of values held by each node pair of the one or more node pairs.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 26, 2020
    Applicant: FUJITSU LIMITED
    Inventor: Takumi Danjo
  • Publication number: 20200195708
    Abstract: An information processing system includes: a first information processing device that transmits first data to be retained via a communication path; a second information processing device that calculates first calculation result data that is a calculation result of the first data received via the communication path and second data to be retained and transmits the calculated first calculation result data via the communication path; a third information processing device that transmits third data to be retained via the communication path; and a fourth information processing device that calculates second calculation result data that is a calculation result of the third data received via the communication path and fourth data to be retained and calculates third calculation result data that is a calculation result of the first calculation result data received via the communication path and the calculated second calculation result data.
    Type: Application
    Filed: October 31, 2019
    Publication date: June 18, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Takumi Danjo, Takashi Arakawa, Masakatsu ITO
  • Publication number: 20170368682
    Abstract: A neural network apparatus includes: a plurality of neuron units each including: an adder that performs addition processing and one or more digital analog converters that perform digital-analog conversion processing, relating to weighted inputs; and a delta-sigma analog digital converter that converts an analog signal indicating an added value obtained by adding all of the weighted inputs obtained from the adder and the one or more digital analog converters, into a pulse signal according to an amplitude, and outputs the pulse signal; a plurality of arithmetic units each of which multiplies the pulse signal outputted from one neuron unit by a weighted value, and outputs a result to another neuron unit; and an oscillator that is capable of changing a frequency of a clock signal to be outputted and supplies the clock signal to the neuron unit and the arithmetic unit according to control from a control unit.
    Type: Application
    Filed: May 26, 2017
    Publication date: December 28, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Takumi Danjo, Hirotaka TAMURA, Sanroku Tsukamoto
  • Publication number: 20170220924
    Abstract: Boltzmann machine includes a plurality of circuit units each having an adder that adds weighted input signals and a comparison unit that compares an output signal of the adder with a threshold signal to output a binary output signal; and digital arithmetic units each generating the weighted input signals by weighting the binary output signal of the circuit units with a weight. The comparison unit has a first comparator that compares a thermal noise with a reference voltage to output a binary digital random signal, a DA converter that converts the digital random signal to an analog random signal and varies a magnitude of the analog random signal, and a second comparator that compares the output signal of the adder with the analog random signal to generate the binary output signal with a predetermined probability function.
    Type: Application
    Filed: January 30, 2017
    Publication date: August 3, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Takumi DANJO, Sanroku TSUKAMOTO, Hirotaka TAMURA
  • Publication number: 20170063363
    Abstract: A comparator includes an input-stage circuit configured to operate in synchronization with a clock signal and to produce two voltages at two nodes, respectively, such that which one of the two voltages is greater than the other is responsive to which one of two input signals is greater than the other, a positive-feedback circuit configured to operate in synchronization with the clock signal and to produce, through positive feedback, two output signals responsive to which one of the two voltages at the two nodes is greater than the other, and an adjustment circuit coupled to the two nodes, and configured to change, in response to a setting value, speed at which voltages at the two nodes change.
    Type: Application
    Filed: August 9, 2016
    Publication date: March 2, 2017
    Applicant: FUJITSU LIMITED
    Inventor: Takumi Danjo
  • Patent number: 9331685
    Abstract: A comparator system includes: a clock node configured to supply a clock signal; a comparator configured to compare a signal of a first input node with a signal of a second input node in synchronization with the clock signal; and a first variable capacitance coupled between the first input node and the clock node.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: May 3, 2016
    Assignee: Fujitsu Limited
    Inventor: Takumi Danjo
  • Publication number: 20150333746
    Abstract: A comparator system includes: a clock node configured to supply a clock signal; a comparator configured to compare a signal of a first input node with a signal of a second input node in synchronization with the clock signal; and a first variable capacitance coupled between the first input node and the clock node.
    Type: Application
    Filed: April 8, 2015
    Publication date: November 19, 2015
    Inventor: Takumi DANJO
  • Patent number: 9154120
    Abstract: An electronic circuit includes: a pair of first transistors in which a first control signal is inputted to at least one of a first control terminal; a comparator circuit that sets electric potentials of a pair of differential output terminals based on an electric current flowing through the pair of first transistors; second transistors that are coupled in series in a path between an electric power source and a node from at least one of the pair of differential output terminals and between the corresponding pair of first transistors, and having a second control terminals to which a second control signal is inputted; first switches that are respectively coupled in series to the second transistors in the path and that are turned ON in synchronization with a clock signal; and a generation circuit that generates the second control signal based on the clock signal.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: October 6, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Takumi Danjo
  • Patent number: 9093965
    Abstract: A folded cascode amplifier circuit includes: an input stage having a pair of transistors and configured to output a positive phase intermediate signal and an opposite phase intermediate signal; a cascode amplification stage having pairs of transistors connected in multiple stages, to which the positive phase intermediate signal and the opposite phase intermediate signal are supplied, and which is configured to output a positive phase output signal and an opposite phase output signal, which are differential signals; a first capacitor connected between a signal line of the positive phase intermediate signal and a signal line of the opposite phase output signal; and a second capacitor connected between a signal line of the opposite phase intermediate signal and a signal line of the positive phase output signal.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: July 28, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Takumi Danjo
  • Publication number: 20150029049
    Abstract: An electronic circuit includes: a pair of first transistors in which a first control signal is inputted to at least one of a first control terminal; a comparator circuit that sets electric potentials of a pair of differential output terminals based on an electric current flowing through the pair of first transistors; second transistors that are coupled in series in a path between an electric power source and a node from at least one of the pair of differential output terminals and between the corresponding pair of first transistors, and having a second control terminals to which a second control signal is inputted; first switches that are respectively coupled in series to the second transistors in the path and that are turned ON in synchronization with a clock signal; and a generation circuit that generates the second control signal based on the clock signal.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 29, 2015
    Inventor: Takumi DANJO
  • Patent number: 8890740
    Abstract: A comparator has a comparator circuit to output an output voltage based on a voltage difference between a first and second input voltage, a variable capacitor connected to an output terminal, an input voltage control circuit to generate a common voltage and add the common voltage to the first and the second input voltages, and a correction circuit to control the variable capacitor to control the common voltage. The correction circuit controls a first capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a first voltage difference, and controls a second capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a second voltage value, and controls the common voltage so that a difference between the first capacitance value and the second capacitance value becomes equal to a predetermined capacitance value.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: November 18, 2014
    Assignees: Fujitsu Limited, Fujitsu Semiconductor Limited
    Inventors: Masanori Hoshino, Takumi Danjo
  • Publication number: 20140292410
    Abstract: A folded cascode amplifier circuit includes: an input stage having a pair of transistors and configured to output a positive phase intermediate signal and an opposite phase intermediate signal; a cascode amplification stage having pairs of transistors connected in multiple stages, to which the positive phase intermediate signal and the opposite phase intermediate signal are supplied, and which is configured to output a positive phase output signal and an opposite phase output signal, which are differential signals; a first capacitor connected between a signal line of the positive phase intermediate signal and a signal line of the opposite phase output signal; and a second capacitor connected between a signal line of the opposite phase intermediate signal and a signal line of the positive phase output signal.
    Type: Application
    Filed: February 12, 2014
    Publication date: October 2, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Takumi Danjo
  • Patent number: 8836376
    Abstract: A comparator includes: a differential amplifier of which operational state is switched in response to a clock-signal, and which outputs a first intermediate-output corresponding to a first input-signal and a second intermediate-output corresponding to a second input-signal; a differential latch circuit of which operational state is switched in response to the clock-signal, and a state of which is changed depending on the first intermediate-output and the second intermediate-output; a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output; and a second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: September 16, 2014
    Assignee: Fujitsu Limited
    Inventor: Takumi Danjo