Patents by Inventor Takuo Sugano

Takuo Sugano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6734501
    Abstract: A fully inverted type SOI-MOSFET has a channel region 18 constructed of a portion that belongs to a top silicon layer 13 and is located just under a gate electrode 15 and a source region 16 and a drain region 17, which belong to the top silicon layer 13 and are located adjacent to this channel region 18. The channel region 18 is inverted throughout the entire thickness during operation. The source region 16 has a source resistance RS, which satisfies a relation that (1/gm)>RS with respect to the mutual conductance gm of the channel region 18 itself. According to this fully inverted type SOI-MOSFET, the effective mutual conductance (Gm) can be increased.
    Type: Grant
    Filed: January 29, 2002
    Date of Patent: May 11, 2004
    Assignees: Sharp Kabushiki Kaisha
    Inventors: Takuo Sugano, Toru Toyabe, Tatsuro Hanajiri, Akira Saito, Yoshiro Akagi
  • Publication number: 20030118064
    Abstract: The invention provides a laser and a method for the production thereof by which it is possible to fabricate a device on a Si substrate, and to fabricate further an optical device such as an optical memory on the Si substrate. The laser has an Er-doped nano-ultrafine crystalline Si waveguide formed on the Si substrate wherein the Er-doped nano-ultrafine crystalline Si layer is co-doped with oxygen to result in a structure in which Er ion is surrounded by at least one or more oxygen atom(s).
    Type: Application
    Filed: December 4, 2002
    Publication date: June 26, 2003
    Applicant: Riken
    Inventors: Xinwei Zhao, Shuji Komuro, Hideo Isshiki, Yoshinobu Aoyagi, Takuo Sugano
  • Publication number: 20020100938
    Abstract: A fully inverted type SOI-MOSFET has a channel region 18 constructed of a portion that belongs to a top silicon layer 13 and is located just under a gate electrode 15 and a source region 16 and a drain region 17, which belong to the top silicon layer 13 and are located adjacent to this channel region 18. The channel region 18 is inverted throughout the entire thickness during operation. The source region 16 has a source resistance RS, which satisfies a relation that (1/gm)>RS with respect to the mutual conductance gm of the channel region 18 itself. According to this fully inverted type SOI-MOSFET, the effective mutual conductance (Gm) can be increased.
    Type: Application
    Filed: January 29, 2002
    Publication date: August 1, 2002
    Inventors: Takuo Sugano, Toru Toyabe, Tatsuro Hanajiri, Akira Saito, Yoshiro Akagi
  • Patent number: 6353330
    Abstract: A single-flux-quantum digital device includes a first superconducting line extended in a large ring, a second superconducting line connected to the first superconducting line, a superconducting single electron transistor for regulating a supercurrent flowing through the second superconducting line, and a small tunnel junction device for detecting a change in the supercurrent flowing through the first superconducting line. The first superconducting line is extended in a large ring. The second superconducting line divides the large ring into two small rings which are substantially the same in shape and area. The small tunnel junction device is connected to a point where the first and the second superconducting line are joined.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: March 5, 2002
    Assignee: Riken
    Inventors: Akinobu Kanda, Koji Ishibashi, Yoshinobu Aoyagi, Takuo Sugano
  • Patent number: 4790903
    Abstract: An intermittent etching process for forming efficiently by reactive ion etching (RIE), a minute recess, such as a groove having an opening width as small as about 0.1 .mu.m, with a large aspect ratio in layers of metals, semiconductors, etc. The process comprises alternating RIE steps of brief duration e.g. 30 seconds with vacuumizing for evacuating gaseous reaction products produced in the RIE step from the etched recess. The process is particularly suitable for formation of a bridging portion of Nb, etc. constituting Josephson devices, by making use of three layered resist technique.
    Type: Grant
    Filed: March 18, 1988
    Date of Patent: December 13, 1988
    Assignee: University of Tokyo
    Inventors: Takuo Sugano, Hideharu Miyake
  • Patent number: 4678945
    Abstract: A superconducting logic circuit has a first and a second one-junction SQUID's (superconducting quantum interference device) connected by a superconducting inductor, the junction of the second SQUID having a larger critical current than that of the first SQUID, the inductance of the second SQUID being smaller than that of the inductor, and a signal applied to the first SQUID is unidirectionally transmitted to the second SQUID by applying bias currents to the junctions of the two SQUID's.
    Type: Grant
    Filed: February 14, 1985
    Date of Patent: July 7, 1987
    Assignee: University of Tokyo
    Inventors: Takuo Sugano, Yoichi Okabe, Hideharu Miyake, Naoki Fukaya
  • Patent number: 4469527
    Abstract: A semiconductor substrate is formed by irradiating a semiconductor substrate with radioactive ray so as to generate lattice defects therein for making the entire substrate semi-insulating and then rendering only the surface of the thus irradiated substrate semiconductive, so that a semiconductor device is produced by using the substrate thus formed.
    Type: Grant
    Filed: December 1, 1981
    Date of Patent: September 4, 1984
    Assignee: Tokyo University
    Inventors: Takuo Sugano, Ho Q. Vu
  • Patent number: 4352726
    Abstract: An ion selective field-effect sensor selectively sensitive to a particular cation to be measured is disclosed. In the sensor is used a giant heterocyclic compound selectively forming a complex with the particular cation as an ion sensitive film provided on a surface of a field-effect semiconductor device.
    Type: Grant
    Filed: October 28, 1980
    Date of Patent: October 5, 1982
    Assignee: Takashi Mukaibo
    Inventors: Takuo Sugano, Eiji Niki, Yoichi Okabe, Tatsuo Akiyama
  • Patent number: 4015893
    Abstract: An isolation zone for light transmission is formed in a compound semiconductor optical integrated circuit by selective oxidation of a compound semiconductor surface by oxygen plasma.
    Type: Grant
    Filed: August 25, 1975
    Date of Patent: April 5, 1977
    Assignee: Kentaro Hayashi, President, University of Tokyo
    Inventors: Takuo Sugano, Yoshifumi Mori
  • Patent number: 3935328
    Abstract: Method for providing dielectric isolation of an epitaxial layer of a compound semiconductor or for providing separation and protection of pn-junction of a compound semiconductor by applying plasma oxidation.
    Type: Grant
    Filed: October 11, 1973
    Date of Patent: January 27, 1976
    Assignee: Kentaro Hayashi
    Inventors: Takuo Sugano, Yoshifumi Mori