Patents by Inventor Takuya Fukuda

Takuya Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150100147
    Abstract: After a forward end of a workpiece is inserted into a through-hole and fitting is started, a follow operation of moving the workpiece to follow the shape of the through-hole is performed during the movement of the workpiece in a fitting direction. At this time, the workpiece is fitted into the through-hole while a control point of a robot is changed in a direction opposite to the fitting direction according to the amount of movement of the workpiece in the fitting direction.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 9, 2015
    Applicant: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Tetsuro IZUMI, Yukio HASHIGUCHI, Takuya FUKUDA, Ryoichi NAGAI
  • Publication number: 20140259615
    Abstract: A production system includes: a plurality of production robots configured to share and perform processing works on a workpiece; a controller configured to control the processing works by the plurality of production robots; and a conveying member configured to convey the workpiece between the plurality of production robots. The controller is configured to: acquire work-delay information on a first production robot in which a processing work is delayed compared with a predetermined processing time; acquire work-ready information on a second production robot that can substitutively perform the processing work being performed by the first production robot; and convey the workpiece from the first production robot to the second production robot using the conveying member based on a result of cross-checking the work-delay information and the work-ready information.
    Type: Application
    Filed: March 18, 2014
    Publication date: September 18, 2014
    Applicant: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Takuya FUKUDA, Shingo ANDO
  • Publication number: 20140271061
    Abstract: A manufacturing system includes a first robot cell apparatus including a first manufacturing robot and a first rack to which the first manufacturing robot is fixed, a second robot cell apparatus including a second manufacturing robot and a second rack to which the second manufacturing robot is fixed, the second robot cell apparatus being disposed adjacent to the first robot cell apparatus, and a transport path setter that sets a transport path of a transport robot that performs at least one of receiving a workpiece from the first robot cell apparatus and supplying a workpiece component to the first robot cell apparatus. A space through which the transport robot is movable is provided under each of the first and second racks, and the transport path setter sets the transport path of the transport robot so that the transport path passes through at least one of the spaces.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 18, 2014
    Applicant: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Takuya FUKUDA, Shingo ANDO
  • Publication number: 20140169925
    Abstract: In a system for transferring a plate-shaped member with interleaving paper thereon, a suction adhesion device included in a suction adhesion unit includes suction pads that adhere to a surface of a glass plate by suction with interleaving paper in between the surface and the suction pads; an air blowing device blows air between the adhered glass plate and a glass plate positioned below the adhered glass plate; a robot moves the suction adhesion unit; a clamping device includes a pair of pushing members that are arranged at both sides, respectively, of the glass plates and move toward the glass plates to come close to each other; and at least before the suction adhesion unit lifts the adhered glass plate, a controller causes the pair of pushing members to move to push protruding portions of pieces of interleaving paper, the protruding portions protruding from the sides of the glass plates.
    Type: Application
    Filed: May 16, 2012
    Publication date: June 19, 2014
    Applicant: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Kenji Bando, Takuya Fukuda, Akifumi Wakisaka
  • Publication number: 20140121837
    Abstract: A robot system includes a robot arm, one or more actuators that are provided in the robot arm to drive the robot arm, a sensor unit that detects an external force applied to at least one of the robot arm and the actuators, and a controller that controls an operation of each of the actuators and limits a torque instruction value for each of the actuators on the basis of a detection result of the sensor unit.
    Type: Application
    Filed: January 8, 2014
    Publication date: May 1, 2014
    Applicant: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Yukio HASHIGUCHI, Shingo ANDO, Takuya FUKUDA, Takenori OKA, Shinji MURAI, Takeomi HIDAKA, Manabu OKAHISA
  • Patent number: 8650965
    Abstract: A robot according to an embodiment includes an arm, a strain sensor, one or more actuator, and a sensor fixing jig. The strain sensor includes a piezoelectric body that has a natural frequency higher than a natural frequency of a structural material forming the arm. The one or more actuators are provided in the arm to drive the arm. The sensor fixing jig is provided in a base of the actuator, among the actuators in the arm, closest to a base end of the arm. The strain sensor is provided in the sensor fixing jig.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: February 18, 2014
    Assignee: Kabushiki Kaisha Yaskawa Denki
    Inventors: Yukio Hashiguchi, Shingo Ando, Takuya Fukuda, Takenori Oka, Shinji Murai, Takeomi Hidaka, Manabu Okahisa
  • Publication number: 20130345848
    Abstract: In this robot system, a control portion includes a workpiece supporting operation command portion, a workpiece positioning operation command portion causing a second robot arm to move a workpiece toward a workpiece fitted portion while causing an end effector of the second robot arm to support the workpiece, and a fitting operation command portion causing a first robot arm to fit the workpiece into the workpiece fitted portion.
    Type: Application
    Filed: February 7, 2013
    Publication date: December 26, 2013
    Applicant: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Tetsuro IZUMI, Yukio HASHIGUCHI, Takuya FUKUDA, Ryoichi NAGAI
  • Publication number: 20120048027
    Abstract: A robot according to an embodiment includes arm and a strain sensor. The strain sensor includes a piezoelectric body that has a natural frequency higher than a natural frequency of a structural material forming the arm.
    Type: Application
    Filed: August 30, 2011
    Publication date: March 1, 2012
    Applicant: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Yukio HASHIGUCHI, Shingo Ando, Takuya Fukuda, Takenori Oka, Shinji Murai, Takeomi Hidaka, Manabu Okahisa
  • Patent number: 7588117
    Abstract: A drive motor mounting structure of an electric vehicle, including: a drive motor unit (12) having its front part attached to a vehicle body member (17) in a front part of a vehicle (10) by use of a front motor mount (27); and a rigid robust member (31) disposed in front of and obliquely above the drive motor unit (12), and above and in front of the front motor mount (27).
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: September 15, 2009
    Assignee: Nissan Motor Co., Ltd.
    Inventor: Takuya Fukuda
  • Publication number: 20070051549
    Abstract: A drive motor mounting structure of an electric vehicle, including: a drive motor unit (12) having its front part attached to a vehicle body member (17) in a front part of a vehicle (10) by use of a front motor mount (27); and a rigid robust member (31) disposed in front of and obliquely above the drive motor unit (12), and above and in front of the front motor mount (27).
    Type: Application
    Filed: April 19, 2004
    Publication date: March 8, 2007
    Applicant: NISSAN MOTOR CO., LTD.
    Inventor: Takuya Fukuda
  • Patent number: 6833331
    Abstract: An SOG film 16 obtained by heat-treating a polysilazan type SOG film at high temperature of about 800° C. is used as a planarized insulating film to be formed on the gate electrode (9; see FIGS. 31 and 32) of a MISFET (Qs, Qn, Qp) A polysilazan SOG film (57) not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers (54, 55, 56, 62, 63).
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: December 21, 2004
    Assignees: Hitachi Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masayoshi Saito, Katsuhiko Hotta, Masayoshi Hirasawa, Masayuki Kojima, Hiroyuki Uchiyama, Hiroyuki Maruyama, Takuya Fukuda
  • Patent number: 6700152
    Abstract: The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: March 2, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Takuya Fukuda, Nobuyoshi Kobayashi, Yoshitaka Nakamura, Masayoshi Saito, Shinichi Fukada, Yoshifumi Kawamoto
  • Patent number: 6638811
    Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: October 28, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masayoshi Saito, Yoshitaka Nakamura, Hidekazu Goto, Keizo Kawakita, Satoru Yamada, Toshihiro Sekiguchi, Isamu Asano, Yoshitaka Tadaki, Takuya Fukuda, Masayuki Suzuki, Tsuyoshi Tamaru, Naoki Fukuda, Hideo Aoki, Masayoshi Hirasawa
  • Publication number: 20030132479
    Abstract: In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.
    Type: Application
    Filed: January 3, 2003
    Publication date: July 17, 2003
    Inventors: Yoshitaka Nakamura, Masayoshi Hirasawa, Isamu Asano, Tsuyoshi Tamaru, Satoru Yamada, Keizo Kawakita, Toshihiro Sekiguchi, Yoshitaka Tadaki, Takuya Fukuda
  • Patent number: 6576946
    Abstract: Capacitors are stretched over a plurality of memory cells in the direction of a bit line in order to effectively utilize spaces between adjacent cells. In addition, by creating a cubic structure of each capacitor by adoption of a self-matching technique, the structure can be utilized more effectively. As a result, it is possible to assure a sufficient capacitor capacitance in spite of a limitation imposed by the fabrication technology and obtain an assurance of sufficient space between cells in a shrunk area of a memory cell accompanying high-scale integration and miniaturization of a semiconductor device.
    Type: Grant
    Filed: July 20, 1999
    Date of Patent: June 10, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Misuzu Kanai, Yuzuru Ohji, Takuya Fukuda, Shinpei Iijima, Ryouichi Furukawa, Yasuhiro Sugawara, Hideharu Yahata
  • Publication number: 20030077896
    Abstract: An SOG film 16 obtained by heat-treating a polysilazan type SOG film at high temperature of about 800° C. is used as a planarized insulating film to be formed on the gate electrode 9 of a MISFET (Qs, Qn, Qp) A polysilazan SOG film 57 not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers (54, 55, 56, 63).
    Type: Application
    Filed: November 26, 2002
    Publication date: April 24, 2003
    Inventors: Masayoshi Saito, Katsuhiko Hotta, Masayoshi Hirasawa, Masayuki Kojima, Hiroyuki Uchiyama, Hiroyuki Maruyama, Takuya Fukuda
  • Patent number: 6509277
    Abstract: An SOG film 16 obtained by heat-treating a polysilazan type SOG film at high temperature of about 800° C. is used as a planarized insulating film to be formed on the gate electrode 9 of a MISFET (Qs, Qn, Qp). A polysilazan SOG film 57 not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers (54, 55, 56, 62, 63).
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: January 21, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masayoshi Saito, Katsuhiko Hotta, Masayoshi Hirasawa, Masayuki Kojima, Hiroyuki Uchiyama, Hiroyuki Maruyama, Takuya Fukuda
  • Publication number: 20020195641
    Abstract: The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.
    Type: Application
    Filed: August 30, 2002
    Publication date: December 26, 2002
    Inventors: Takuya Fukuda, Nobuyoshi Kobayashi, Yoshitaka Nakamura, Masayoshi Saito, Shinichi Fukada, Yoshifumi Kawamoto
  • Publication number: 20020182798
    Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.
    Type: Application
    Filed: May 31, 2002
    Publication date: December 5, 2002
    Inventors: Masayoshi Saito, Yoshitaka Nakamura, Hidekazu Goto, Keizo Kawakita, Satoru Yamada, Toshihiro Sekiguchi, Isamu Asano, Yoshitaka Tadaki, Takuya Fukuda, Masayuki Suzuki, Tsuyoshi Tamaru, Naoki Fukuda, Hideo Aoki, Masayoshi Hirasawa
  • Patent number: 6479899
    Abstract: The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: November 12, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Takuya Fukuda, Nobuyoshi Kobayashi, Yoshitaka Nakamura, Masayoshi Saito, Shinichi Fukada, Yoshifumi Kawamoto